Semiconductor device and method of manufacturing thereof
In order to implement a high-density high-performance semiconductor system small in size, there is provided a method for implementing three-dimensional connection between a plurality of semiconductor chips differing from each other with the shortest metal interconnect length, using penetration electrodes, thereby enabling a fast operation at a low noise level, the method being a three-dimensional connection method very low in cost, and short in TAT in comparison with the known example, capable of bonding at an ordinary temperature, and excellent in connection reliability.
1. A method of manufacturing a semiconductor device, comprising the steps of:
preparing a plurality of semiconductor chips that include a semiconductor chip of an upper tier provided with a first set of bumps and a semiconductor chip of an lower tier provided with a second set of bumps and a first set of through-holes; and a first set of electrodes formed along respective inner wall faces of the first set of through-holes;
preparing an interconnect substrate provided with a resin substrate having a second set of through-holes, an interconnect formed on a face of the resin substrate, and a second set of electrodes formed along respective inner wall faces of the second set of through-holes;
stacking the semiconductor chip of the upper tier on the semiconductor chip of the lower tier by inserting the first set of bumps of the semiconductor chip of the upper tier into the first set of through-holes of the semiconductor chip of the lower tier in such a way that a contact pressure between respective first set of bumps of the semiconductor chip of the upper tier and respective first set of electrodes of the semiconductor chip of the lower tier is caused due to deformation accompanied by plastic flow of the respective first set of bumps of the semiconductor chip of the upper tier; and
stacking the semiconductor chip of the lower tier on the interconnect substrate by inserting the second set of bumps of the semiconductor chip of the lower tier into the second set of through-holes of the interconnect substrate in such a way that a contact pressure between respective second set of bumps of the semiconductor chip of the lower tier and respective second set of electrodes of the interconnect substrate is caused due to deformation accompanied by plastic flow of the respective second set of bumps of the semiconductor chip of the lower tier.