Analog based, state machine controlled, frequency smooth switching method for frequency timing generators
View Patent ↗A method and circuit for performing switching in a frequency timing generator is described. The method includes detecting a request for a new value for a feedback counter or an reference counter, upon which a loading operation is synchronized for the appropriate counter. A time-out order of the feedback counter and the reference counter is determined. Where no time-out order difference is detected therein, a state machine status word function is completed. Where a time-out order difference is detected therein, it is determined which of the reference counter and the feedback counter times out first. Where the reference counter times out first, a constant charge pump current is delivered to a loop filter associated with a phase locked loop to achieve an upward frequency direction. Where the feedback counter times out first, a constant charge pump current is delivered to the loop filter to achieve a downward frequency direction.
1. A method for performing switching in a frequency timing generator, comprising:
detecting a request for a new value for at least one of a feedback counter or a reference counter;
upon said detecting, synchronizing a loading operation for said counter for which a new value is requested;
determining a time-out order of said feedback counter and said reference counter and provided no difference therein, completing a state machine status word function;
upon a difference is detected therein, determining which of said reference counter and said feedback counter times out first;
provided said reference counter times out first, delivering a constant charge pump current to a loop filter associated with a phase locked loop to achieve an upward frequency direction; and
provided said feedback counter times out first, delivering a constant charge pump current to said loop filter to achieve a downward frequency direction.
2. The method as recited in claim 1 further comprising:
upon providing said constant charge pump current, determining said time-out order of said feedback counter and said reference counter;
enabling a phase detector;
changing said charge pump current; and
ending said state machine status word function.
3. The method as recited in claim 1 wherein said constant charge pump current is provided to a node between a resistance and a first capacitance that are arranged together in series, wherein said resistance and first capacitance in series are in parallel with a second capacitance to form a resistive/capacitive network.
4. The method as recited in claim 3 wherein said loop filter comprises said capacitive/capacitive network.
5. The method as recited in claim 3 wherein a nominal charge pump current is provided to said capacitive/capacitive network at a node between said first resistance and said second capacitance.
6. The method as recited in claim 5 wherein said constant charge pump current effectively bypasses said loop filter with respect to said nominal charge pump current.
7. The method as recited in claim 3 wherein said first capacitance has a capacitance value that is higher than said second capacitance.
8. A method for controlling frequency slewing in a phase locked loop system, comprising:
determining a requested frequency change direction in said phase locked loop;
opening said phase locked loop system by disabling a phase detector of said phase locked loop system by delivering a constant charge pump current; and
upon detecting a lock on said requested frequency, determining a lock state associated with said phase locked loop system, wherein said determining a requested frequency change direction comprises determining a time-out order of a feedback counter and a reference counter associated with said phase locked loop system.
9. The method as recited in claim 8 wherein said opening said phase locked loop system comprises inputting said constant charge pump current to a node between a resistance and a first capacitance that are arranged together in series, wherein said resistance and first capacitance in series are in parallel with a second capacitance to form a capacitive/capacitive network.
10. The method as recited in claim 9 wherein said first capacitance has a value that is higher than said second capacitance.
11. The method as recited in claim 8 wherein said determining a lock state associated with said phase locked loop system comprises determining a state machine status word function.
12. A circuit for performing switching in a frequency timing generator, comprising:
a phase locked loop control section comprising:
a charge pump;
a loop filter coupled to receive charge pump current from said charge pump; and
a voltage controlled oscillator coupled to receive a control voltage from said loop filter;
a reference counter for providing a reference frequency input to said charge pump; and
a feedback counter for providing a feedback frequency input to said charge pump, wherein a requested frequency change direction in said phase locked loop control section is determined based upon a time-out order of said feedback counter and said reference counter, wherein said phase locked loop system is opened with application of a constant charge pump current to a node thereof and wherein, upon detecting a lock on said requested frequency, a lock state associated with said phase locked loop system is determined.
13. The circuit as recited in claim 12 wherein, upon said determining said time-out order wherein a time-out order difference is detected therein, a determination is made as to which of said reference counter and said feedback counter times out first.
14. The circuit as recited in claim 13 wherein, upon determining that said reference counter times out first, said constant charge pump current is delivered to said loop filter to achieve an upward frequency direction.
15. The circuit as recited in claim 13 wherein, upon determining that said feedback counter times out first, said constant charge pump current is delivered to said loop filter to achieve a downward frequency direction.
16. The circuit as recited in claim 12 wherein said loop filter comprises:
a resistance;
a first capacitance in series with said resistance to form a first leg of a resistance/capacitance network; and
a second capacitance in parallel with said first leg of a capacitance/capacitance network, wherein said phase locked loop system is opened with an input of said constant charge pump current to a node between a resistance and a first capacitance.
17. The circuit as recited in claim 16 wherein said first capacitance has a value that is higher than said second capacitance.
18. The circuit as recited in claim 12 wherein said lock state associated with said phase locked loop is determined with a state machine status word function.
19. The circuit as recited in claim 18 wherein a phase detector coupled to said charge pump is enabled, said charge pump current is changed, and said state machine status word function is ended upon providing said constant charge pump current and determining said time-out order of said feedback counter and said reference counter.