IP Library Granted Patent US 7,627,740
Granted Patent B2
US 7,627,740 · App. 11/344,403 · Granted Dec 1, 2009

Methods and apparatus for dynamic prediction by software

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Quick Facts
Patent No.
US 7,627,740
App. No.
11/344,403
Granted
Dec 1, 2009
Kind
B2
Abstract

A method, storage medium, processor instruction and processor to for specifying a value in a first portion of a conditional pre-fetch instruction associated with a branch instruction used for effectuating a branch operation, specifying a target instruction address in a second portion of the instruction, evaluating the value to determine whether a condition is met, and pre-fetching one or more instructions starting at the target instruction address into an instruction buffer of the processor when the condition is met, is provided.

Claims (18)

1. A method, comprising:

specifying a value in a first portion of a conditional pre-fetch instruction, the conditional pre-fetch instruction being associated with a branch instruction used for effectuating a branch operation in a processor, the value corresponding to a condition of the branch instruction;

specifying a target instruction address in a second portion in the conditional pre-fetch instruction;

evaluating the value to determine whether a condition is met; and

pre-fetching one or more instructions starting at the target instruction address into an instruction buffer of the processor when the condition is met;

wherein the value in the first portion of the conditional pre-fetch instruction includes information pertaining to whether branching occurred in a prior iteration of the branch instruction.

2. A method, comprising:

specifying a value in a first portion of a conditional pre-fetch instruction, the conditional pre-fetch instruction being associated with a branch instruction used for effectuating a branch operation in a processor, the value corresponding to a condition of the branch instruction;

specifying a target instruction address in a second portion in the conditional pre-fetch instruction;

evaluating the value to determine whether a condition is met; and

pre-fetching one or more instructions starting at the target instruction address into an instruction buffer of the processor when the condition is met; wherein the value in the first portion of the conditional pre-fetch instruction includes information pertaining to whether branching occurred in the prior two iterations of the branch instruction.

3. A method of operating a processor having an instruction cache and using a branch control instruction associated with a conditional pre-fetch instruction, the conditional pre-fetch instruction including a test condition portion and an instruction address portion, the test condition portion corresponding to a condition of the branch control instruction, the method including:

determining if the test condition portion of the conditional pre-fetch instruction evaluates to a TRUE value; and

when the test condition portion of the conditional pre-fetch instruction evaluates to a TRUE value, preloading one or more instructions beginning at an address indicated by the instruction address portion of the conditional pre-fetch instruction into an instruction buffer of the processor;

wherein the test condition portion includes whether branching occurred in an immediately preceding iteration of the branch control instruction.

4. A method of operating a processor having an instruction cache and using a branch control instruction associated with a conditional pre-fetch instruction, the conditional pre-fetch instruction including a test condition portion and an instruction address portion, the test condition portion corresponding to a condition of the branch control instruction, the method including: determining if the test condition portion of the conditional pre-fetch instruction evaluates to a TRUE value; and

when the test condition portion of the conditional pre-fetch instruction evaluates to a TRUE value, preloading one or more instructions beginning at an address indicated by the instruction address portion of the conditional pre-fetch instruction into an instruction buffer of the processor;

wherein the test condition portion includes whether branching occurred in two immediately preceding iterations of the branch control instruction.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 27, 2011
From: SONY NETWORK ENTERTAINMENT PLATFORM INC.
To: SONY COMPUTER ENTERTAINMENT INC.
Reel/Frame 027481/0351 →
CHANGE OF NAME Recorded Dec 26, 2011
From: SONY COMPUTER ENTERTAINMENT INC.
To: SONY NETWORK ENTERTAINMENT PLATFORM INC.
Reel/Frame 027445/0657 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 19, 2009
From: YASUE, MASAHIRO; HATAKEYAMA, AKIYUKI
To: SONY COMPUTER ENTERTAINMENT INC.
Reel/Frame 022426/0854 →