IP Library Granted Patent US 7,844,926
Granted Patent B1
US 7,844,926 · App. 11/345,554 · Granted Nov 30, 2010

Specification window violation identification with application in semiconductor device design

Assignee: Oracle America, Inc.
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Quick Facts
Patent No.
US 7,844,926
App. No.
11/345,554
Granted
Nov 30, 2010
Kind
B1
Abstract

A method for identifying specification window violations for a system is described. The method includes generating a sample set of input parameters. The system is simulated using the sample set to generate an output set. A mathematical model is best-fit to the output set. A set of desirability functions is defined to an out-of-spec condition. The model is then searched using the desirability functions to identify a worst-case data point. The worst-case data point can then be determined as either being within specification or out of specification.

Claims (28)

1. A method for identifying specification window violations for an integrated circuit, the method comprising:

generating a pseudo-random sample set of input parameters for the integrated circuit;

simulating the integrated circuit using the pseudo-random sample set of input parameters to generate an output set;

fitting a mathematical model to the output set;

optimizing the mathematical model by identifying areas where the mathematical model does not fit the output set, and re-fitting the mathematical model after removing a least statistically significant term;

defining a set of desirability functions to an out-of-spec condition, the desirability functions are set based on an analysis of the output set;

searching the mathematical model using the desirability functions to identify a worst-case data point;

determining whether the worst-case data point is within specification or out of specification; and

implementing the worst-case data point for defining an integrated circuit design to be used to make the integrated circuit when the worst-case data point is within specification.

2. The method of claim 1 , further comprising confirming the worst-case data point by simulating the integrated circuit using input parameters defined by the worst-case data point.

3. The method of claim 1 , wherein generating the pseudo-random sample set of input parameters comprises generating a Latin hypercube sample set, wherein the Latin hypercube sample set has uniform factors.

4. The method of claim 1 wherein the simulating is performed using a SPICE tool.

5. The method of claim 1 wherein the fitting is performed using a second order Taylor series expansion.

6. The method of claim 5 wherein the fitting further comprises optimizing the second order Taylor series expansion by analyzing and reducing residuals.

7. A non-transitory machine readable medium embodying program instructions for identifying specification window violations for an integrated circuit, the machine readable medium comprising:

program instructions for generating a pseudo-random sample set of input parameters for the integrated circuit;

program instructions for simulating the integrated circuit using the pseudo-random sample set of input parameters to generate an output set;

program instructions for fitting a mathematical model to the output set;

program instructions for identifying areas where the mathematical model does not fit the output set;

program instructions for re-fitting the mathematical model after removing a least statistically significant term;

program instructions for searching the model using desirability functions to identify a worst-case data point, the desirability functions are set based on an analysis of the output set;

program instructions for determining whether the worst-case data point is within specification or out of specification; and

program instructions for implementing the worst-case data point for defining an integrated circuit design to be used to make the integrated circuit when the worst-case data point is within specification.

8. The machine readable medium of claim 7 , further comprising program instructions for confirming whether the worst-case data point is within specification by simulating the integrated circuit using input parameters defined by the worst-case data point.

9. The machine readable medium of claim 7 , wherein the program instructions for generating the pseudo-random sample set of input parameters comprises program instructions for generating a Latin hypercube sample set, wherein the Latin hypercube sample set has uniform in factors.

10. The machine readable medium of claim 7 , wherein the program instructions for simulating is a SPICE tool.

11. The machine readable medium of claim 7 , wherein the program instructions for fitting generate a second order Taylor series expansion.

12. The machine readable medium of claim 11 , wherein the program instructions for fitting further comprise program instructions for optimizing the second order Taylor series expansion by analyzing and reducing residuals.

Assignments (2)
MERGER AND CHANGE OF NAME Recorded Dec 16, 2015
From: ORACLE USA, INC.; SUN MICROSYSTEMS, INC.; ORACLE AMERICA, INC.
To: ORACLE AMERICA, INC.
Reel/Frame 037306/0556 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2006
From: RUSSELL, EDMUND L.
To: SUN MICROSYSTEMS, INC.
Reel/Frame 017525/0369 →