Commutating phase selector
View Patent ↗A phase selector for selecting a differential output is provided. The phase selector can include two matched transistor circuits. A first transistor circuit can receive a first differential input signal whereas a second transistor circuit can receive a second differential input signal. One of the transistor circuits can be used to dump an output current generated by the first differential input signal to Vdd. The other transistor circuit can be used to steer an output current generated by the second differential input signal to two output lines, thereby providing a differential output signal on the output lines.
1. A method of operating a phase selector including a first transistor circuit and a second transistor circuit, the method comprising:
determining control signals for the first and second transistor circuits;
based on a first set of the control signals for the first transistor circuit, using the first transistor circuit to dump an output current generated by a first differential input signal to Vdd; and
based on a second set of the control signals for the second transistor circuit, using the second transistor circuit to steer an output current generated by a second differential input signal to output lines, thereby providing a differential output signal to the output lines.
2. The method of claim 1 , further including commutating phase selection by providing a gradual transition of a control signal from a first logic value to a second logic value.
3. The method of claim 2 , wherein commutating phase selection includes gradually turning on at least a first transistor and gradually turning off at least a second transistor.
4. The method of claim 3 , wherein a first period associated with turning on the at least first transistor is equal to a second period associated with turning off the at least second transistor.
5. The method of claim 4 , wherein the first and second periods span several cycles of an input signal comprising the first and second differential input signals.
6. The method of claim 5 , wherein the several cycles include at least two cycles.
7. A phase selector comprising:
means for selectively dumping an output current generated by a first differential input signal to Vdd responsive to a first set of control signals; and
means for selectively steering an output current generated by a second differential input signal to output lines of the phase selector, thereby providing a differential output signal to the output lines responsive to a second set of said control signals,
wherein the means for dumping and the means for selectively steering are connected to the output lines of the phase selector.
8. The phase selector of claim 7 , further including means for providing a gradual transition of a control signal from a first logic value to a second logic value, the control signal being provided to the means for selectively steering.
9. The phase selector of claim 8 , wherein the means for providing a gradual transition includes a state machine or computer-implementable program instructions for gradually turning on at least a first transistor and gradually turning off at least a second transistor.
10. A state machine or a machine-readable medium comprising a computer-implementable program for operating a phase selector, the phase selector including a first transistor circuit and a second transistor circuit, the program comprising:
data for determining control signals for the first and second transistor circuits;
data for using the first transistor circuit to dump an output current generated by a first differential input signal to Vdd responsive to a first set of control signals; and
data for using the second transistor circuit to steer an output current generated by a second differential input signal to output lines of the phase selector responsive to a second set of said control signals, thereby providing a differential output signal to the output lines.