Thin film transistor array panel and manufacturing method thereof

1. A method of manufacturing a thin film transistor array panel, the method comprising:

forming a gate line including a gate electrode on a substrate;

forming a gate insulating layer on the gate line;

forming a semiconductor layer on the gate insulating layer;

forming an ohmic contact layer on the semiconductor layer;

forming a data line including a source electrode and a drain electrode on the ohmic contact layer;

depositing a conductive film on the data line and the drain electrode;

forming a first photoresist on the conductive film;

etching the conductive film using the first photoresist as a mask to form a pixel electrode at least connected to the drain electrode;

depositing a passivation layer; and

removing the first photoresist and a portion of the passivation layer thereon simultaneously to form a passivation member,

wherein the gate insulating layer and the semiconductor layer are simultaneously etched, and

wherein a boundary of a portion of the passivation layer disposed directly on a top surface of the drain electrode faces a boundary of the pixel electrode.

2. The method of claim 1 , wherein a portion of the passivation layer deposited on the first photoresist removed with the first photoresist.

3. The method of claim 1 , wherein a portion of the substrate and a portion of the drain electrode are exposed.

4. The method of claim 3 , wherein the exposed portions of substrate and the drain electrode are enclosed by the gate line and the data line.

5. The method of claim 1 , wherein a portion of the pixel electrode contacts an exposed portion of the substrate.

6. The method of claim 1 , wherein the formation of the pixel electrode comprises forming contact assistants on the gate line and the data line.

7. The method of claim 1 , wherein the formation of the semiconductor layer and the formation of the data line comprise:

depositing the gate insulating layer, the semiconductor layer an intrinsic a-Si layer, the ohmic contact layer an extrinsic a-Si layer, and a conductive layer in sequence, wherein the semiconductor layer is an intrinsic a-Si layer, and the ohmic contact layer is an extrinsic a-Si layer;

forming a second photoresist on the conductive layer, having different thicknesses on different portions of the conductive layer;

selectively etching the conductive layer, the semiconductor layer , and the ohmic contact layer using the second photoresist as a mask;

etching the second photoresist to form a third photoresist; and

selectively etching the data line, the semiconductor layer, and the ohmic contact layer using the third photoresist as a mask to form the data line, the source electrode, the drain electrode, and the ohmic contact layer.

8. The method of claim 7 , wherein the second photoresist is formed by using a photomask including a light blocking area, a translucent area, and a light transmitting area.

9. The method of claim 8 , wherein an ashing process is executed to form the third photoresist.

10. The method of claim 9 , wherein the ashing process is executed until a portion of the second photoresist facing the translucent area of the photomask is removed.

11. The method of claim 1 , wherein the data line and the drain electrode include molybdenum or chromium.

12. The method of claim 1 , wherein the pixel electrode includes indium tin oxide, amorphous indium tin oxide, or indium zinc oxide.

13. The method of claim 1 , further comprising forming a storage electrode line with the same layer as the gate line.

14. The method of claim 13 , wherein the pixel electrode and the storage electrode line are overlapped to each other via the drain electrode.

15. The method of claim 1 , wherein the gate insulating layer has the substantially same planar shape as the semiconductor.

16. The method of claim 1 , wherein there is a gap between the passivation layer and the pixel electrode, and the gap exposes a portion of a top surface of the drain electrode.