Dynamic memory for a cellular terminal
View Patent ↗A DRAM and its application to a mobile telephony circuit with a control circuit including a first refreshment controller controlled by a first clock signal and a second refreshment controller controlled by a second clock signal having a frequency less than that of the first one and used to synchronize events of the GSM network.
1. A circuit for controlling a DRAM in a mobile telephone or cellular terminal apparatus, the circuit comprising:
a first refreshment controller controlled by a first clock signal having a first frequency; and
a second refreshment controller controlled by a second clock signal generated by the mobile telephone or cellular terminal apparatus, a second frequency of the second clock signal being a synchronization frequency of a mobile telephone network protocol.
2. The circuit of claim 1 , wherein the first refreshment circuit is activated in a normal operation mode and the second refreshment circuit is activated in a standby mode of the circuit.
3. The circuit of claim 2 , wherein the second frequency synchronizes a switching between the normal operation mode and the standby mode.
4. The circuit of claim 3 , comprising at least two voltage regulators respectively dedicated to the normal operation mode and the standby mode.
5. The circuit of claim 1 , further comprising the DRAM.
6. A mobile telephony circuit comprising at least one microprocessor, peripherals and modems associated with the at least one microprocessor, and the circuit of claim 5 .
7. A mobile telephone or cellular terminal apparatus, comprising:
at least one microprocessor;
at least one modem associated with the at least one microprocessor for communicating with a GSM network;
a DRAM; and
a circuit for controlling the DRAM, the circuit comprising:
a first refreshment controller controlled by a first clock signal having a first frequency; and
a second refreshment controller controlled by a second clock signal having a second frequency lower than the first frequency;
wherein the second frequency corresponds to a synchronization frequency of the GSM network.
8. The circuit of claim 6 , further comprising a signal processor.
9. The circuit of claim 8 , wherein the signal processor is associated with a second DRAM.
10. A mobile phone comprising the telephony circuit of claim 6 .
11. A method for controlling a DRAM in a mobile telephone or cellular terminal apparatus, the method comprising:
refreshing the DRAM during a first operating mode with a first clock signal having a first frequency;
receiving from the mobile telephone or cellular terminal apparatus a second clock signal having a second frequency, the second frequency being a synchronization frequency of a mobile telephone network protocol; and
refreshing the DRAM during a second operating mode with the second clock signal.