Resolver arrangement

1. A resolver arrangement for detecting the rotational position of a rotor with respect to a stator, wherein the rotor carries a rotor coil and the stator has a pair of stator coils mutually shifted by 90°, and a carrier signal is applied to the rotor coil, the arrangement comprising a carrier signal generator and two processing channels each of which has an analog input connected a different one of the stator coils and a channel output; each of said processing channels comprising:

a sigma-delta modulator with an output that supplies a bit-stream representative of an analog input signal received from a respective stator coil;

a first digital filter that receives the bit-stream from the sigma-delta modulator and converts the bit-stream to intermediate digital data-words;

a digital synchronous demodulator that demodulates the intermediate digital data-words in synchronism with the carrier signal providing demodulated data-words; and

a second digital filter that averages the demodulated data-words and supplies digital output data-words on said channel output, the carrier signal being suppressed in said output data-words.

2. The resolver arrangement according to claim 1 , wherein a clock signal used in the sigma-delta modulator is applied to a clock input of the digital filter in the same processing channel.

3. The resolver arrangement according to any of claim 2 , wherein the first digital filter operates at a first over-sampling rate, the second digital filter operates at a second over-sampling rate and the digital output data-words are provided at a data rate equal to the frequency of the clock signal divided by the product of the first and second over-sampling rates.

4. The resolver arrangement according to claim 3 , wherein the first over-sampling rate is selected between 4 to 256, preferably at 128, the frequency of the clock signal is selected between 10 and 16 MHz and the second over-sampling rate is selected between 4 and 256, preferably at 32.

5. The resolver arrangement according to claim 1 , wherein each processing channel has an overall periodic notch filter characteristic and the frequency of the carrier signal is selected to fall into a notch.

6. The resolver arrangement according to any of claim 1 , wherein the digital filter is a Sinc n filter and the sigma-delta modulator is of (n-1) order.

7. The resolver arrangement according to claim 6 , wherein n=3.

8. The resolver arrangement according to any of claim 1 , wherein the carrier signal generator supplies a pulse width modulated signal representative of a sine signal and susceptible of being applied to the rotor coil through a low-pass filter.

9. The resolver arrangement according to any of claim 1 , wherein each processing channel has means for detecting an offset in the respective analog input signal and correcting means for correcting the intermediate digital data-words to compensate for a detected offset.

10. The resolver arrangement according to any of claim 1 , wherein the second digital filter is a digital integrator.

11. The resolver arrangement according to any of claim 1 , wherein the first and second digital filters of both processing channels are all integrated in a CMOS component.

12. The resolver arrangement according to any of claim 1 , wherein the digital filters are configurable both with respect to the order of the filter function and the over-sampling rate.