Semiconductor circuit, driving circuit of electro-optical device, and electronic apparatus

1. A semiconductor circuit comprising:

a logic circuit block that sequentially shifts and outputs a signal to be output to scanning lines in synchronization with a clock signal, the logic circuit block including a clock control circuit, a clock generating circuit, a unit shift circuit, a bidirectional transfer circuit, a NAND circuit, and an inverter circuit;

an external interface circuit block including a level shift circuit that boosts a low-amplitude signal from the logic circuit block to a high-amplitude signal and a buffer circuit that drives the scanning lines; and

power wiring lines that supply a plurality of reference potentials,

wherein the logic circuit block and the external interface circuit block are both connected to a common power wiring line that is one of the power wiring lines and supplies a common reference potential,

the current consumption of the logic circuit block and the external interface circuit block are different, and

a width of the common power wiring line that is supplied to the logic circuit block being different than a width of the common power wiring line that is supplied to the external interface circuit block with a width of each wiring formed according to the current consumption respectively.

2. An electro-optical device comprising:

a display area which has a plurality of scanning lines and a plurality of data lines;

switching units which are formed to correspondingly connect the scanning lines and the data lines in the display area;

pixel electrodes which are arranged to correspond to the switching units; and

a driving circuit;

wherein the driving circuit includes a logic circuit block, an external interface circuit block, and power wiring lines that supply a plurality of reference potentials, the logic circuit block sequentially shifting and outputting a signal to be output to scanning lines in synchronization with a clock signal and including a clock control circuit, a clock generating circuit, a unit shift circuit, a bidirectional transfer circuit, a NAND circuit, and an inverter circuit, the external interface circuit block including a level shift circuit that boosts a low-amplitude signal from the logic circuit block to a high-amplitude signal and a buffer circuit that drives the scanning lines,

wherein the logic circuit block and the external interface circuit block are both connected to a common power wiring line that is one of the power wiring lines and supplies a common reference potential, the current consumption of the logic circuit block and the external interface circuit block are different, and a width of the common power wiring line that is supplied to the logic circuit block is different than a width of the common power wiring line that is supplied to the external interface circuit block with a width of each wiring formed according to the current consumption respectively.

3. The driving circuit of an electro-optical device according to claim 2 ,

wherein the logic circuit block has a shift register including the unit shift circuit that, in synchronization with a clock signal, transmits a signal to be output to the scanning lines or the data lines.

4. The driving circuit of an electro-optical device according to claim 2 ,

wherein the logic circuit block has a shift register including the unit shift circuit that, in synchronization with a clock signal, transmits a signal to be output to the scanning lines or the data lines; and

wherein the clock control circuit controls supply of the clock signal to the unit shift circuit based on a judgment of whether data to be transmitted has a significant level.

5. The driving circuit of an electro-optical device according to claim 2 ,

wherein the logic circuit block has a shift register including the unit shift circuit that, in synchronization with a clock signal, transmits a signal to be output to the scanning lines or the data lines, and

wherein the buffer circuit outputs a signal to be input from an external circuit for driving the driving circuit of an electro-optical device to the logic circuit block with a signal rising and falling time in a predetermined range.

6. The driving circuit of an electro-optical device according to claim 2 ,

wherein the logic circuit block has a shift register including the unit shift circuit that, in synchronization with a clock signal, transmits a signal to be output to the scanning lines or the data lines, and

wherein the external interface circuit block has a DA converter circuit for driving the data lines with a predetermined potential.

7. The driving circuit of an electro-optical device according to claim 2 ,

wherein a first driving voltage, which is a difference between a maximum and a minimum from the plurality of reference potentials to be supplied to the logic circuit block, is different from a second driving voltage, which is a difference between a maximum and a minimum from the plurality of reference potentials to be supplied to the external interface circuit block.

8. An electro-optical device comprising, on the same substrate:

the driving circuit according to claim 2 ;

the plurality of scanning lines and the plurality of data lines;

the switching units that are correspondingly connected to the scanning lines and the data lines; and

the pixel electrodes that are correspondingly connected to the switching units.

9. The electro-optical device according to claim 8 ,

wherein a potential to be supplied to the common power wiring line is different from a ground potential which is supplied to the electro-optical device.

10. An electronic apparatus comprising according to claim 8 .

11. A semiconductor circuit comprising:

a plurality of power wiring lines supplying a plurality of reference potentials,

a logic circuit block connected to a first power wiring line of the plurality of power wiring lines and including a clock control circuit, a clock generating circuit, a unit shift circuit, a bidirectional transfer circuit, a NAND circuit, and an inverter circuit; and

an external interface circuit block connected to the first power wiring line of the plurality of power wiring lines and including a level shift circuit that boosts a low-amplitude signal from the logic circuit block to a high-amplitude signal and a buffer circuit that drives the scanning lines;

wherein the first power wiring line supplies a common reference potential to the logic and external interface circuit blocks, and

wherein a width of the first power wiring line in the logic circuit block is different than a width of the first power wiring line in the external interface circuit block.

12. The semiconductor circuit of claim 1 , wherein a width of the common power wiring line varies based on a diagonal screen size.

13. The semiconductor circuit of claim 1 , wherein a width of the common power wiring line supplied to the logic circuit is smaller than a width of the common power wiring line supplied to the external interface circuit when a diagonal screen size is smaller than approximately twelve inches.

14. The semiconductor circuit of claim 1 , wherein a width of the common power wiring line supplied to the external interface circuit is larger than a width of the common power wiring line supplied to the logic circuit when a diagonal screen size is larger than approximately twelve inches.

15. The driving circuit of an electro-optical device according to claim 2 , wherein a width of the common power wiring line varies based on a diagonal screen size.

16. The driving circuit of an electro-optical device according to claim 2 , wherein a width of the common power wiring line supplied to the logic circuit is smaller than a width of the common power wiring line supplied to the external interface circuit when a diagonal screen size is smaller than approximately twelve inches.

17. The driving circuit of an electro-optical device according to claim 2 , wherein a width of the common power wiring line supplied to the external interface circuit is larger than a width of the common power wiring line supplied to the logic circuit when a diagonal screen size is larger than approximately twelve inches.

18. The semiconductor circuit of claim 11 , wherein a width of the first power wiring line varies based on a diagonal screen size.

19. The semiconductor circuit of claim 11 , wherein a width of the first power wiring line supplied to the logic circuit is smaller than a width of the first power wiring line supplied to the external interface circuit when a diagonal screen size is smaller than approximately twelve inches.

20. The semiconductor circuit of claim 11 , wherein a width of the first power wiring line supplied to the external interface circuit is larger than a width of the first power wiring line supplied to the logic circuit when a diagonal screen size is larger than approximately twelve inches.