IP Library Patent Application 11350812
Patent Application
App. No. 11/350,812

Conductive polymers for the electroplating

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Quick Facts
Patent No.
US None
App. No.
11/350,812
Abstract

A process to produce ultra-small structures of between ones of nanometers to hundreds of micrometers in size, in which the structures are compact, nonporous and exhibit smooth vertical surfaces. Such processing is accomplished using a non-conductive or semi-conductive substrate on which a layer of a conductive material, such as a conductive polymer, is applied, and on which a second layer of a masking material, such as a pattern resist material, is applied. Following patterning of the second resist layer, and either the full or partial etching of the conductive polymer, or alternatively omitting the step of etching the conductive layer, electroplating techniques will be used to produce ultra-small structures on the substrate or alternatively directly on the conductive layer, after which either all of remaining portions of the conductive polymer layer and the resist layer will be removed, or only the resist layer will be removed, or alternatively neither will be removed.

Claims (67)

1 . A method of patterning ultra-small structures on a surface, comprising:

providing a substrate;

forming a first, conductive layer on the substrate;

forming a second layer on said first conductive layer;

defining and forming a desired pattern in said second layer;

removing selected portions of the conductive layer as defined by the patterned second layer thereby exposing portions of the substrate; and

growing ultra-small structures on the exposed portions of said substrate in an electroplating process.

2 . The method of claim 1 wherein said ultra-small structures are comprised of a material selected from the group consisting silver (Ag), nickel (Ni), copper (Cu), aluminum (Al), gold (Au) and platinum (Pt).

3 . The method of claim 1 wherein said electroplating process uses pulsed electroplating techniques and further comprises the step of applying a series of voltage pulses comprising at least one positive voltage pulse, wherein each said at least one voltage pulse is between 1.5 and 12 volts, and each said at least one voltage pulse lasts for less than 1 microsecond.

4 . The method of claim 3 wherein each said at least one voltage pulse is for a period of less than 500 ns.

5 . The method of claim 3 further comprising:

after said step of applying, resting for a rest period of at least 1 microsecond, and then repeating said applying step.

6 . The method of claim 5 wherein the rest period is between 1 microsecond and 500 ms.

7 . The method of claim 1 wherein said second layer is comprised of photoresist.

8 . The method of claim 1 wherein said first conductive layer is comprised of polypheneylene (PPV).

9 . The method of claim 1 wherein said first conductive layer is comprised of methano [70] fullerene, (MDMO).

10 . The method of claim 1 wherein said first conductive layer is selected from the group consisting of polypheneylene (PPV), methano [70] fullerene, (MDMO), Poly(3-methylthiophene) (pMeT), Poly(dithiono[3,4-b:3′,4′-d]thiophene) (pDTT1), Poly(3-p-fluorophenylthiophene) (pFPT), PEDT-Poly(ethylene-dioxythiophene), Plyaniline, Polythiophene, and Polypyrrole.

11 . The method of claim 1 including the further step of removing the first conductive layer and second layer material from around said ultra-small structures.

12 . The method of claim 1 wherein said first conductive layer is a conductive polymer.

13 . The method of claim 1 wherein said first conductive layer is a non-metallic conductor.

14 . The method of claim 1 further including the step of removing the first conductive layer and the second layer from around said ultra-small structures and from said non-conductive substrate.

15 . A method for patterning ultra-small features on a non-conductive surface comprising:

providing a non-conductive substrate;

forming a conductive layer on said non-conductive surface;

depositing a layer of photoresist on said conductive layer;

defining a pattern in said photoresist layer;

etching desired portions of said conductive layer as defined by the patterned photoresist layer to thereby expose a portion of the non-conductive substrate;

growing said ultra-small structures on the exposed portion of said non-conductive surface in an electroplating process; and

removing the remaining portions of said conductive layer and said photoresist layer.

16 . The method of claim 15 wherein said conductive layer is selected from the group consisting of polypheneylene (PPV), methano [70] fullerene, (MDMO), Poly(3-methylthiophene) (pMeT), Poly(dithiono[3,4-b:3 ′,4′-d]thiophene) (pDTT1), Poly(3-p-fluorophenylthiophene) (pFPT), PEDT-Poly(ethylene-dioxythiophene), Plyaniline, Polythiophene, and Polypyrrole.

17 . The method of claim 15 wherein said electroplating process is a pulse-electroplating process.

18 . The method of claim 17 wherein said pulse-electroplating process includes a step of applying a series of voltage pulses comprising at least one positive voltage pulse, wherein each said at least one voltage pulse lasts for less than 1 microsecond.

19 . The method of claim 18 wherein each said at least one voltage pulse period is less than 500 ns.

20 . The method of claim 18 wherein said pulse-electroplating process includes:

after said step of applying, resting for a rest period of at least 1 microsecond, and then repeating said applying step.

21 . The method of claim 18 wherein each said at least one voltage pulse is between 1.5 and 12 volts.

22 . The method of claim 18 wherein the series of voltage pulses further comprises at least one negative voltage pulse.

23 . A method for patterning ultra-small features on a semi-conductive surface comprising:

providing a semi-conductive surface having a conducting layer formed thereon;

depositing a mask layer on said conductive layer;

defining a pattern in said mask layer;

etching desired portions of said conductive layer as defined by the patterned mask layer to thereby expose portions of the semi-conductive layer there beneath;

growing said ultra-small structures on exposed said semi-conductive surface in a pulse-electroplating process; and

removing the remaining portions of the conductive layer and the mask layer from the semi-conductive substrate and the ultra-small structures.

24 . The method of claim 23 wherein said ultra-small structures are comprised of a material selected from the group consisting of silver (Ag), nickel (Ni), copper (Cu), aluminum (Al), gold (Au) and platinum (Pt).

25 . The method of claim 23 wherein said pulse-electroplating process comprises the step of applying a series of voltage pulses comprising at least one positive voltage pulse, wherein each said at least one voltage pulse is between 1.5 and 12 volts, and each said at least one voltage pulse lasts for less than 1 microsecond.

26 . The method of claim 25 wherein each said at least one voltage pulse is for a period of less than 500 ns.

27 . The method of claim 26 further comprising:

after said step of applying, resting for a rest period of at least 1 microsecond, and then repeating said applying step.

28 . The method of claim 27 wherein said rest period is 1 microsecond to 500 ms.

29 . The method of claim 23 wherein said mask layer is comprised of photoresist.

30 . The method of claim 25 , wherein the series of voltage pulses further comprises at least one negative voltage pulse.

31 . The method of claim 1 wherein the step of removing selected portions of the first conductive layer includes leaving a portion of the first conductive layer so that the substrate is not exposed.

32 . The method of claim 1 wherein the step of removing selected portions of the first conductive layer includes the step of completely removing the first conductive layer so that an upper surface of the substrate is exposed.

33 . The method of claim 32 including the further step of depositing a thin adhesion layer on the exposed upper surface of the substrate.

34 . The method of claim 33 wherein the adhesion layer comprises nickel.

35 . The method of claim 1 wherein the substrate is non-conductive.

36 . The method of claim 1 wherein the substrate is semi-conductive.

37 . A method of patterning ultra-small structures on a surface, comprising:

providing a substrate;

forming a first, conductive layer on the substrate;

forming a second layer on said first conductive layer;

defining and forming a desired pattern in said second layer by removing portions thereof to expose surface portions of the first conductive layer; and

growing ultra-small structures on the exposed surface portions of the first conductive layer in an electroplating process.

38 . The method of claim 37 including the additional step of removing additional portions of the first conductive layer on which there are no ultra-small structures.

39 . The method of claim 37 wherein the substrate is comprised of a non-conductive material.

40 . The method of claim 37 wherein the substrate is comprised of a semi-conductive material.

Assignments (3)
NUNC PRO TUNC ASSIGNMENT Recorded Oct 9, 2012
From: APPLIED PLASMONICS, INC.
To: ADVANCED PLASMONICS, INC.
Reel/Frame 029095/0525 →
NUNC PRO TUNC ASSIGNMENT Recorded Oct 3, 2012
From: VIRGIN ISLAND MICROSYSTEMS, INC.
To: APPLIED PLASMONICS, INC.
Reel/Frame 029067/0657 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 31, 2006
From: GORRELL, JONATHAN; DAVIDSON, MARK
To: VIRGIN ISLANDS MICROSYSTEMS, INC.
Reel/Frame 017719/0614 →