Integrated circuit and processing system with improved power source monitoring and methods for use therewith
View Patent ↗A processing system includes a direct current to direct current (DC-DC) converter for generating a supply voltage when coupled to a battery. A memory module stores a plurality of operational instructions. A processing module receives power from the DC-DC converter and executes the plurality of operational instructions. A power monitor circuit monitors the power source and powers down the power source when a first error condition is detected in the power source.
1. A processing system comprising:
a direct current to direct current (DC-DC) converter configured to generate a supply voltage when coupled to a battery;
a memory module configured to store a plurality of operational instructions;
a processing module, operatively coupled to the memory module, that is configured to execute the plurality of operational instructions, the processing module receiving power from the DC-DC converter; and
a power monitor circuit, operatively coupled to the DC-DC converter, that is distinct from and in communication with the processing module and that is configured to monitor the DC-DC converter and to power down the DC-DC converter and the processing module when a first error condition is detected in the DC-DC converter.
2. The processing system of claim 1 wherein the plurality of operational instructions include a disable routine for disabling the power monitor circuit.
3. The processing system of claim 2 wherein the disable routine is executed as part of a power-up sequence for the processing module.
4. The processing system of claim 1 wherein the power monitor circuit is further configured to monitor the supply voltage and to power down the DC-DC converter when a second error condition is detected in the DC-DC converter.
5. The processing system of claim 4 wherein the power monitor circuit is further configured to power down the processing module when the second error condition is detected.
6. The processing system, of claim 4 wherein the power monitor circuit is further configured to modify a processing module parameter when a third error condition is detected.
7. The processing system of claim 4 wherein the second error condition includes one of: a low voltage condition, a rapid voltage drop, and a voltage spike.
8. The processing system of claim 1 wherein the power monitor circuit is further configured to power down the processing module prior to powering down the DC-DC converter to thereby preserve at least one processing module state that can be recovered during a subsequent restart of the processing module.
9. The processing system of claim 1 wherein the first error condition includes one of: a low voltage condition, a rapid voltage drop, and a voltage spike.
10. The processing system of claim 1 wherein the processing system is implemented on an integrated circuit, and wherein the power monitor circuit is an on-chip power monitor circuit.
11. An integrated circuit comprising:
a power source configured to generate a supply voltage;
a memory module configured to store a plurality of operational instructions;
a processing module, operatively coupled to the memory module, that is configured to execute the plurality of operational instructions, the processing module receiving power from the power source; and
a power monitor circuit, distinct from and operatively coupled to the processing module and the power source, that is configured to monitor the power source and to power down the processing module and the power source when a first error condition is detected in the power source.
12. The integrated circuit of claim 11 wherein the plurality of operational instructions include a disable routine for disabling the power monitor circuit.
13. The integrated circuit of claim 12 wherein the disable routine is executed as part of a power-up sequence for the processing module.
14. The integrated circuit of claim 11 wherein the power monitor circuit is further configured to monitor the power source and for powering down the processing module when a second error condition is detected in the power source.
15. The integrated circuit of claim 14 wherein the power monitor circuit is further configured to modify a processing module parameter when a third error condition is detected.
16. The integrated circuit of claim 14 wherein the second error condition includes one of: a low voltage condition, a rapid voltage drop, and a voltage spike.
17. The integrated circuit of claim 11 wherein the power monitor circuit is further configured to power down the processing module prior to powering down the DC-DC converter to thereby preserve at least one processing module state that can be recovered during a subsequent restart of the processing module.
18. The integrated circuit of claim 11 wherein the first error condition includes one of: a low voltage condition, a rapid voltage drop, and a voltage spike.
19. The integrated circuit of claim 11 wherein the processing module and memory module are implemented on a digital portion of the system on a chip integrated circuit.
20. The integrated circuit of claim 11 wherein the power source includes a direct current-to-direct current (DC-DC) converter.
21. The integrated circuit of claim 20 wherein the power monitor circuit powers down the DC-DC converter.
22. The integrated circuit of claim 20 wherein the power monitor circuit powers down the integrated circuit.
23. A method comprising:
powering up a power source in response to a user event to thereby provide power to a processing module of an integrated circuit;
monitoring the power source using an on-chip power monitor circuit of the integrated circuit; and
powering down the power source and the processing module from the on-chip power monitor circuit when a first error condition is detected in the power source.
24. The method of claim 23 further comprising: executing an on-chip disable routine of the integrated circuit for disabling the power monitor circuit.
25. The method of claim 24 further comprising: executing a power monitor routine for monitoring the power source and for powering down the processing module when a second error condition is detected in the power source.
26. The method of claim 25 wherein the disable routine is executed after the power monitor routine is initiated.
27. The method of claim 25 wherein the power monitor routine includes operational instructions to modify a processing module parameter when a third error condition is detected.
28. The method of claim 25 wherein the power monitor routine includes operational instructions to preserve at least one processing module state that can be recovered during a subsequent restart of the processing module.
29. The method of claim 25 wherein the second error condition includes one of: a low voltage condition, a rapid voltage drop, and a voltage spike.
30. The method of claim 25 wherein the first error condition is the same as the second error condition.
31. The method of claim 25 wherein the first error condition differs from the second error condition.