Controlling an accumulation of timing errors in a synchronous system

1. Apparatus for communicating clock correction data between a plurality of clocked entities using a clock correction unit, comprising:

a source-native pre-scaler for converting a plurality of source-native clock correction values to a plurality of scaled source-native clock correction values, said pre-scaler multiplying each source-native clock correction value by a factor N 1 ;

a source-native divider for dividing an adjusted source-native clock correction value by a value M 1 to produce a standard quotient and a standard remainder, said standard quotient defining a standard clock correction value;

a source-native accumulator for accumulating a sum comprised of at least one of said scaled source-native clock corrections and said standard remainder produced from said source-native divider, said sum defining said adjusted source-native clock correction value; and

a communication link for communicating each said standard clock correction value from a first clocked entity to a second clocked entity.

2. The apparatus according to claim 1 , further comprising a consumer-native pre-scaler for converting a plurality of said standard clock correction values to a plurality of scaled standard clock correction values, said consumer-native pre-scaler multiplying each standard clock correction value by a factor N 2 .

3. The apparatus according to claim 2 , further comprising a consumer-native divider for dividing an adjusted standard clock correction value by a value M 2 to produce a consumer quotient and a consumer remainder, said consumer quotient defining a consumer-native clock correction value.

4. The apparatus according to claim 3 , further comprising a standard accumulator for accumulating an accumulator sum comprised of at least one of said scaled standard clock correction values and said consumer remainder produced from said consumer-native divider, said accumulator sum defining said adjusted standard clock correction value.

5. The apparatus according to claim 1 , wherein each said first and said second clocked entity are selected from the group consisting of a synchronous data terminal, a data communications portion of a synchronous data communication radio, and a modem portion of a synchronous data communication radio.

6. The apparatus according to claim 1 , further comprised of a common clock, wherein a local clock rate for said first clocked entity and said second clocked entity are derived from said common clock.

7. The apparatus according to claim 1 , further comprising a communication link for communicating each said source-native clock correction value to a timing adjustment system associated with said first clocked entity.

8. A method for communicating clock correction data between a plurality of clocked entities using a clock correction unit, comprising:

converting a plurality of source-native clock correction values to a plurality of scaled source-native clock correction values by multiplying each source-native clock correction value by a factor N 1 ;

dividing an adjusted source-native clock correction value by a value M 1 to produce a standard quotient and a standard remainder, said standard quotient defining a standard clock correction value;

accumulating a sum comprised of at least one of said scaled source-native clock corrections and said standard remainder produced from said source-native divider, said sum defining said adjusted source-native clock correction value; and

communicating each said standard clock correction value from a first clocked entity to a second clocked entity.

9. The method according to claim 8 , further comprising converting a plurality of said standard clock correction values to a plurality of scaled standard clock correction values by multiplying each standard clock correction value by a factor N 2 .

10. The method according to claim 9 , further comprising dividing an adjusted standard clock correction value by a value M 2 to produce a consumer quotient and a consumer remainder, said consumer quotient defining a consumer-native clock correction value.

11. The method according to claim 10 , further comprising accumulating a sum comprised of at least one of said scaled standard clock correction values and said consumer remainder produced from said consumer-native divider, said sum defining said adjusted standard clock correction value.

12. The method according to claim 8 , further comprising selecting each said first and said second clocked entity from the group consisting of a synchronous data terminal, a data communications portion of a synchronous data communication radio, and a modem portion of a synchronous data communication radio.

13. The method according to claim 8 , further comprising deriving a local clock rate for said first clocked entity and said second clocked entity from a common clock.

14. The method according to claim 8 , further comprising communicating each said source-native clock correction value to a timing adjustment system associated with said first clocked entity.

15. A machine readable storage media, having stored thereon a computer program having a plurality of code sections executable by a machine for causing the machine to perform the steps of:

converting a plurality of source-native clock correction values to a plurality of scaled source-native clock correction values by multiplying each source-native clock correction value by a factor N 1 ;

dividing an adjusted source-native clock correction value by a value M 1 to produce a standard quotient and a standard remainder, said standard quotient defining a standard clock correction value;

accumulating a sum comprised of at least one of said scaled source-native clock corrections and said standard remainder produced from said source-native divider, said sum defining said adjusted source-native clock correction value; and

communicating each said standard clock correction value from a first clocked entity to a second clocked entity.