Technique for generating input stimulus to cover properties not covered in random simulation
View Patent ↗A design of an integrated circuit is first verified using directed and/or random test cases. For a cover directive not covered by the directed and/or random test cases, a property is created, where a simulation trace that causes the property to fail covers the cover directive. Thereafter, the property is evaluated, and dependent on the evaluation, the simulation trace is dumped and stored for subsequent exercising of the cover directive.
1. A method of verifying a design of an integrated circuit, comprising:
at least one of simulating a plurality of random test cases for the design and simulating a plurality of directed test cases for the design;
identifying a cover directive not covered by the simulating the plurality of random tests and the simulating the plurality of directed test cases;
creating a property dependent on the identifying, wherein constraints are applied to one or more inputs or internal signals of the design, and a simulation trace that causes the property to fail covers the cover directive;
evaluating the property; and
storing the simulation trace based on the evaluating;
wherein the property being defined as a sum of !C, !A 1 , !A 2 , and !A i ,
C comprises a condition being tested, and
A 1 ,A 2 , and A i represent constraints that each evaluate high when passing.
2. The method of claim 1 , further comprising:
running the simulation trace to cover the cover directive.
3. The method of claim 1 , wherein storing the simulation trace occurs in response to the property evaluating as failing.
4. The method of claim 1 , wherein the simulation trace is not stored in response to the property evaluating as passing.
5. The method of claim 1 , further comprising:
expressing the simulation trace as a test bench; and
adding the test bench to a regression suite for the design.
6. The method of claim 1 , evaluating the property comprising:
testing a condition of the design.
7. A computer system, comprising:
a processor;
a memory operatively connected to the processor; and
instructions residing in the memory and executable by the processor, the instructions comprising instructions to:
at least one of simulate a plurality of random test cases for a design of an integrated circuit and simulate a plurality of directed test cases for the design,
identify a cover directive not covered by the simulation of the plurality of random tests and the simulation of the plurality of directed test cases,
create a property dependent on the identification, wherein constraints are applied to one or more inputs or internal signals of the design, and a simulation trace that causes the property to fail covers the cover directive,
evaluate the property, and
store the simulation trace based on the evaluation;
wherein the property being defined as a sum of !C, !A 1 , !A 2 , and !A i ,
C comprises a condition being tested, and
A 1 , A 2 , A i represent constraints that each evaluate high when passing.
8. The computer system of claim 7 , further comprising instructions to:
run the simulation trace to cover the cover directive.
9. The computer system of claim 7 , wherein storing the simulation trace occurs in response to the property evaluating as failing.
10. The computer system of claim 7 , wherein the simulation trace is not stored in response to the property evaluating as passing.
11. The computer system of claim 7 , further comprising instructions to:
express the simulation trace as a test bench; and
add the test bench to a regression suite for the design.
12. The computer system of claim 7 , wherein the instructions to evaluate the property comprise instructions to:
test a condition of the design.
13. A computer-readable medium having instruction therein, the instructions for:
at least one of simulating a plurality of random test cases for a design of an integrated circuit and simulating a plurality of directed test cases for the design;
identifying a cover directive not covered by the simulating the plurality of random tests and the simulating the plurality of directed test cases;
creating a property dependent on the identifying, wherein constraints arc applied to one or more inputs or internal signals of the design, and a simulation trace that causes the property to fail covers the cover directive;
evaluating the property; and
storing the simulation trace based on the evaluating;
wherein the property being defined as a sum of !C, !A 1 , !A 2 , and !A i ,
C comprises a condition being tested, and
A 1 , A 2 , and A i , represent constraints that each evaluate high when passing.
14. The computer-readable medium of claim 13 , further comprising instructions for:
running the simulation trace to cover the cover directive.
15. The computer-readable medium of claim 13 , wherein storing the simulation trace occurs in response to the property evaluating as failing.
16. The computer-readable medium of claim 13 , further comprising instructions for:
expressing the simulation trace as a test bench; and
adding the test bench to a regression suite for the design.
17. The computer-readable medium of claim 13 , the instructions for evaluating the property comprising instructions for:
testing a condition of the design.