I/O-based enforcement of multi-level computer operating modes
A computer is architected so that a monitoring and enforcement of an operating policy is carried out at an interface circuit that transmits data between a processor and one or more function blocks. The function blocks may include system memory, a display, a network, a USB port, or a non-volatile memory. Since the interface circuit handles every transaction between the processor and its supported function blocks, the interface circuit is an effective point at which to enforce limited performance modes when the computer's usage is not in compliance with the operating policy.
1 . A computer adapted for operation in an unrestricted use mode and a limited function mode comprising:
a processor;
a plurality of functional circuits; and
a support circuit coupled to the processor and at least one of the plurality of functional circuits, the support circuit comprising:
an interface for managing data communication between the processor and the at least one of the plurality of the functional circuits;
a state function reflecting a compliance status and for sending a signal activating a limited function operating mode; and
an enforcement function for adjusting the interface to impede effective performance of the at least one of the plurality of functional circuits responsive to the signal to activate the limited function operating mode.
2 . The computer of claim 1 , wherein the limited function mode is selected from a set of limited function modes comprising one of:
a) entering a payment;
b) configuring a network connection;
c) retrieving data;
d) disabling the computer but allowing user entry of a recovery code; and
e) disabling the computer and requiring authorized service technician intervention.
3 . The computer of claim 2 , wherein the enforcement function enables the selected limited function mode by controlling at least one of input/output access and memory availability.
4 . The computer of claim 2 , wherein the state function comprises a metering function and wherein the enforcement function selects the limited function mode from the set of limited function modes responsive to a signal from the metering function indicating a level of enforcement.
5 . A method of limiting the performance of a computer comprising:
monitoring for a trigger event corresponding to activating a restricted mode of operation;
selecting a restricted mode of operation of the computer from a set of restricted modes of operation responsive to the trigger event;
activating the selected restricted mode of operation by limiting an effectiveness of a function at an interface circuit that couples the function to a processor.
6 . The method of claim 5 , wherein the function comprises at least one of a system memory function, a display function, a non-volatile memory access function, a Universal Serial Bus, and a network interface function.
7 . The method of claim 5 , wherein the function is a system memory function and limiting the effectiveness of the function comprises limiting system memory to less than 25% of a normally available system memory.
8 . The method of claim 5 , wherein the function is a system memory function and limiting the effectiveness of the function comprises limiting system memory to a fixed amount of memory available for processing, wherein a more severe limiting of functionality is achieved by lowering the fixed amount of memory available for processing.
9 . The method of claim 5 , wherein the function is a display function and limiting the effectiveness of the function comprises at least one of reducing a number of pixels available for displaying information, reducing the color depth/spectrum available, and automatically halting the display signal at the end of an interval.
10 . The method of claim 5 , wherein the function is a non-volatile memory access function and limiting the effectiveness of the function comprises at least one of limiting the non-volatile memory size available, limiting data access to read-only, limiting data access to write-only, limiting data access speed, and limiting data access accumulated size per powerup/reset.
11 . The method of claim 5 , wherein the function is a non-volatile memory access function and limiting the effectiveness of the function comprises limiting data access to read at full speed and write at a rate less than 10% of the read rate.
12 . The method of claim 5 , wherein the function is a non-volatile memory access function and limiting the effectiveness of the function comprises providing limited access to data files and no access to executable files.
13 . The method of claim 5 , wherein the function is a non-volatile memory access function and limiting the effectiveness of the function comprises limiting data access to read-only at a restricted data rate compared to a data rate available during normal operation.
14 . The method of claim 5 , wherein the function is a network interface function and limiting the effectiveness of the function comprises one of blocking access to a network, limiting a data transfer speed, and limiting a total data transferred during a period of time.
15 . The method of claim 5 , wherein the function is a Universal Serial Bus and limiting the effectiveness of the function comprises limiting a data transfer over the USB to write only.
16 . A support circuit in a computer for processing signals carrying data between a processor and at least one function block of the computer comprising:
a plurality of bi-directional busses for sending and receiving data;
an interface circuit for processing and routing the signals among the plurality of busses;
an execution environment for monitoring compliance to an operating policy and enforcing the operating policy when the computer is not in compliance with the operating policy.
17 . The support circuit of claim 16 , wherein the execution environment comprises an enforcement circuit coupled to the interface circuit, wherein the enforcement circuit causes the interface circuit to limit processing and routing of the signals among the plurality of busses.
18 . The support circuit of claim 16 , wherein the execution environment comprises a cryptographic function for use in processing messages received at the execution environment.
19 . The support circuit of claim 16 , wherein the execution environment activates a limited function mode of the computer selected from a set of limited function modes, the selection corresponding to a degree of non-compliance with the operating policy.
20 . The support circuit of claim 16 , wherein the execution environment comprises a port for signaling an external enforcement function when the computer is not in compliance with the operating policy.