Interconnect design for reducing radiated emissions
View Patent ↗An interconnect system between an integrated circuit device and a printed circuit board may include a filter between the integrated circuit device and the power subsystem of the printed circuit board. The filter may be a low-pass filter that reduces current in a higher frequency range without negatively modifying current in a lower frequency range and may reduce radiated emissions produced during operation of the integrated circuit. The filter may be implemented by arranging core-power voltage conductors and ground conductors at a first or second level interconnect into one or more voltage groupings and one or more adjacent ground groupings such that series inductance is increased. In some embodiments, the first level interconnect may include conductive bumps or pads between an integrated circuit and a substrate. In some embodiments, the second level interconnect may include solder balls, pins, pads, or other conductors of a package, socket, or interposer.
1. A computer system, comprising:
one or more printed circuit boards, wherein one of the printed circuit boards comprises a power subsystem;
an integrated circuit device comprising a die and a package, wherein the die is coupled to the package at a first level interconnect, and wherein the package is coupled to the one of the one or more printed circuit boards at a second level interconnect; and
a power distribution bus connecting the power subsystem to the integrated circuit device;
wherein at least one of the first or second level interconnects comprises a plurality of power supply voltage conductors and a plurality of ground conductors, wherein the plurality of power supply voltage conductors comprises one or more voltage groups, wherein the plurality of ground conductors comprises one or more ground groups, and wherein at least one of the voltage groups and an adjacent one of the ground groups are arranged so as to implement a low pass filter between the die and the power subsystem of the printed circuit board; and
wherein the power supply voltage conductors of the at least one of the voltage groups and the ground conductors of the adjacent one of the ground groups are arranged in such a way as to create a higher series inductance at the at least one of the first or second level interconnects than an arrangement comprising an alternating pattern of power supply voltage conductors and ground conductors having equal spacing between each pair of adjacent power supply voltage and ground conductors.
2. The computer system of claim 1 , wherein the adjacent one of the ground groups is patterned to surround the at least one of the voltage groups.
3. The computer system of claim 1 , wherein the at least one of the voltage groups and the adjacent one of the ground groups are separated by an amount greater than a spacing between conductors within the at least one of the voltage groups or the adjacent one of the ground groups.
4. The computer system of claim 1 , wherein the at least one of the voltage groups and the adjacent one of the ground groups provide power supply voltage and ground interconnections between the die and the package.
5. The computer system of claim 1 , wherein the at least one of the voltage groups and the adjacent one of the ground groups provide power supply voltage and ground interconnections between the package and a socket containing the integrated circuit device coupled to the printed circuit board.
6. The computer system of claim 1 , wherein the at least one of the voltage groups and the adjacent one of the ground groups provide power supply voltage and ground interconnections between a socket containing the integrated circuit device and the printed circuit board.
7. An integrated circuit device, comprising:
a die; and
a package;
wherein the die is coupled to the package at a first level interconnect;
wherein the package is configured for coupling to a printed circuit board at a second level interconnect;
wherein at least one of the first or second level interconnects comprises a plurality of power supply voltage conductors and a plurality of ground conductors, wherein the plurality of power supply voltage conductors comprises one or more voltage groups, wherein the plurality of ground conductors comprises one or more ground groups, and wherein at least one of the voltage groups and an adjacent one of the ground groups are arranged so as to implement a low pass filter between the die and a power subsystem when the integrated circuit device is in operation; and
wherein the adjacent one of the ground groups is patterned to surround the at least one of the voltage groups.
8. The integrated circuit device of claim 7 , wherein the power supply voltage conductors of the at least one of the voltage groups and the ground conductors of the adjacent one of the ground groups are arranged in such a way as to create a higher series inductance at the at least one of the first or second level interconnects than an arrangement comprising an alternating pattern of power supply voltage conductors and ground conductors having equal spacing between each pair of adjacent power supply voltage and ground conductors.
9. The integrated circuit device of claim 7 , wherein the at least one of the voltage groups and the adjacent one of the ground groups are separated by an amount greater than a spacing between conductors within the at least one of the voltage groups or the adjacent one of the ground groups.
10. The integrated circuit device of claim 7 , wherein the at least one of the voltage groups and adjacent ones of the ground groups comprise a plurality of pairs of voltage groups and adjacent ground groups.
11. The integrated circuit device of claim 7 , wherein the plurality of power supply voltage conductors and the plurality of ground conductors are implemented as conductive bumps or pads on said die.
12. The integrated circuit device of claim 7 , wherein the plurality of power supply voltage conductors and the plurality of ground conductors are implemented as pins, solder balls, or pads on said package.
13. The integrated circuit device of claim 7 , further comprising a socket;
wherein the package is coupled to the socket;
wherein the socket is configured to be coupled to a printed circuit board; and
wherein one of the at least one of the voltage groups and the adjacent one of the ground groups provide power supply voltage and ground interconnections at the second level interconnect through the socket.
14. An integrated circuit device, comprising a die;
wherein the die comprises a plurality of power supply voltage conductors and a plurality of ground conductors;
wherein the plurality of power supply voltage conductors comprises one or more voltage groups, wherein the plurality of ground conductors comprises one or more ground groups, and wherein at least one of the voltage groups and an adjacent one of the ground groups are arranged so as to implement a low pass filter between the die and a power subsystem when the integrated circuit device is in operation; and
wherein the at least one of the voltage groups and the adjacent one of the ground groups are separated by an amount greater than a spacing between conductors within the at least one of the voltage groups or the adjacent one of the ground groups.
15. The integrated circuit device of claim 14 , wherein the power supply voltage conductors of the at least one of the voltage groups and the ground conductors of the adjacent one of the ground groups are arranged in such a way as to create a higher series inductance between the die and the power subsystem than an arrangement comprising an alternating pattern of power supply voltage conductors and ground conductors having equal spacing between each pair of adjacent power supply voltage and ground conductors.
16. The integrated circuit device of claim 14 , wherein the at least one of the voltage groups and adjacent ones of the ground groups comprise a plurality of pairs of voltage groups and adjacent ground groups, and wherein the plurality of pairs of voltage groups and adjacent ground groups are patterned to implement greater spacing between a voltage group and an adjacent ground group of each pair than a spacing between conductors within the voltage group or the adjacent ground group of each pair.
17. The integrated circuit device of claim 14 , wherein the plurality of power supply voltage conductors and the plurality of ground conductors are implemented as conductive bumps.
18. The computer system of claim 1 , wherein the at least one of the voltage groups and adjacent ones of the ground groups comprise a plurality of pairs of voltage groups and adjacent ground groups, and wherein the plurality of pairs of voltage groups and adjacent ground groups are patterned to implement greater spacing between a voltage group and an adjacent ground group of each pair than a spacing between conductors within the voltage group or the adjacent ground group of each pair.
19. The integrated circuit device of claim 10 , wherein the plurality of pairs of voltage groups and adjacent ground groups are patterned to implement greater spacing between a voltage group and an adjacent ground group of each pair than a spacing between conductors within the voltage group or the adjacent ground group of each pair.
20. The integrated circuit device of claim 14 , wherein the adjacent one of the ground groups is patterned to surround the at least one of the voltage groups.