IP Library Granted Patent US 7,716,686
Granted Patent B1
US 7,716,686 · App. 11/354,392 · Granted May 11, 2010

System, method and computer program product for interface hooking

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Quick Facts
Patent No.
US 7,716,686
App. No.
11/354,392
Granted
May 11, 2010
Kind
B1
Abstract

A system, method and computer program product are provided. In use, a holding instruction is inserted. After inserting the holding instruction, the hooking of an interface is completed.

Claims (37)

1. A hooking method, comprising:

inserting a holding instruction into interface code that has not yet been hooked by utilizing a processor; and

after inserting the holding instruction, completing the hooking of an interface; wherein the holding instruction holds operation of the interface such that there is a delay before the hooking of the interface is completed;

wherein the holding instruction holds any execution that arrives at the holding instruction for allowing the hooking of the interface to be completed without disruption;

wherein the holding instruction is inserted after a yield operation for allowing modified code which has already started execution to complete, such that disruption of the modified code in a form of a race condition where interference between a thread associated with the hooking of the interface and the modified code is avoided; wherein after the yield operation, the completion of the hooking is concluded by replacing the holding instruction with a second portion of hook code, the second portion of hook code inserted after a first portion of hook code to constitute an entirety of hook code to be inserted; and

wherein the holding instruction includes a relative jump instruction that operates to jump to a location of a jump instruction.

2. The method of claim 1 , wherein the yield operation is performed.

3. The method of claim 2 , wherein the hooking of the interface is completed, after the yield operation is performed.

4. The method of claim 2 , wherein the yield operation includes a sleep instruction.

5. The method of claim 1 , wherein the holding instruction is inserted with an atomic operation.

6. The method of claim 1 , wherein it is determined whether the holding instruction would cross a memory boundary.

7. The method of claim 6 , wherein the holding instruction is conditionally inserted based on the determination.

8. The method of claim 6 , wherein the holding instruction is conditionally inserted past the memory boundary based on the determination.

9. The method of claim 6 , wherein the memory boundary includes a cache memory boundary.

10. The method of claim 1 , wherein the completing the hooking of the interface includes inserting the first portion of hook code after the holding instruction.

11. The method of claim 1 , wherein the interface includes an application program interface (API).

12. The method of claim 1 , wherein the interface is hooked for security purposes.

13. The method of claim 1 , wherein the interface is hooked for countering terrorism.

14. The method of claim 1 , wherein the holding instruction is inserted in a location where the hooking of the interface is to take place.

15. A hooking computer program product embodied on a computer readable memory, comprising:

computer code for inserting a holding instruction into interface code that has not yet been hooked; and

computer code for completing an operation, after inserting the holding instruction;

wherein the holding instruction holds operation of an interface such that there is a delay before a hooking of the interface is completed;

wherein the holding instruction holds any execution that arrives at the holding instruction for allowing the hooking of the interface to be completed without disruption;

wherein the hooking computer program product is operable such that the holding instruction is inserted after a yield operation for allowing modified code which has already started execution to complete, such that disruption of the modified code in a form of a race condition where interference between a thread associated with the hooking of the interface and the modified code is avoided;

wherein the hooking computer program product is operable such that after the yield operation, the completion of the hooking is concluded by replacing the holding instruction with a second portion of hook code, the second portion of hook code inserted after a first portion of hook code to constitute an entirety of hook code to be inserted; and

wherein the holding instruction includes a relative jump instruction that operates to jump to a location of a jump instruction.

16. A system, comprising:

a processor;

a computer-executable holding instruction; and

a computer-executable hooking application for completing a hooking of an interface utilizing the processor, after inserting the holding instruction;

wherein the holding instruction holds operation of the interface such that there is a delay before the hooking of the interface is completed;

wherein the system is operable such that the holding instruction is inserted into interface code that has not yet been hooked;

wherein the holding instruction holds any execution that arrives at the holding instruction for allowing the hooking of the interface to be completed without disruption;

wherein system is operable such that the holding instruction is inserted after a yield operation for allowing modified code which has already started execution to complete, such that disruption of the modified code in a form of a race condition where interference between a thread associated with the hooking of the interface and the modified code is avoided;

wherein system is operable such that after the yield operation, the completion of the hooking is concluded by replacing the holding instruction with a second portion of hook code, the second portion of hook code inserted after a first portion of hook code to constitute an entirety of hook code to be inserted; and

wherein the holding instruction includes a relative jump instruction that operates to jump to a location of a jump instruction.

Assignments (10)
CORRECTIVE ASSIGNMENT TO CORRECT THE THE PATENT TITLES AND REMOVE DUPLICATES IN THE SCHEDULE PREVIOUSLY RECORDED AT REEL: 059354 FRAME: 0335. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jun 23, 2022
From: MCAFEE, LLC
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 060792/0307 →
SECURITY INTEREST Recorded Mar 3, 2022
From: MCAFEE, LLC
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT AND COLLATERAL AGENT
Reel/Frame 059354/0335 →
RELEASE OF INTELLECTUAL PROPERTY COLLATERAL - REEL/FRAME 045056/0676 Recorded Mar 2, 2022
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MCAFEE, LLC
Reel/Frame 059354/0213 →
RELEASE OF INTELLECTUAL PROPERTY COLLATERAL - REEL/FRAME 045055/0786 Recorded Oct 26, 2020
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MCAFEE, LLC
Reel/Frame 054238/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENT 6336186 PREVIOUSLY RECORDED ON REEL 045056 FRAME 0676. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Oct 22, 2020
From: MCAFEE, LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 054206/0593 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENT 6336186 PREVIOUSLY RECORDED ON REEL 045055 FRAME 786. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Oct 22, 2020
From: MCAFEE, LLC
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 055854/0047 →
SECURITY INTEREST Recorded Jan 12, 2018
From: MCAFEE, LLC
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 045055/0786 →
SECURITY INTEREST Recorded Jan 12, 2018
From: MCAFEE, LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 045056/0676 →
CHANGE OF NAME AND ENTITY CONVERSION Recorded Aug 24, 2017
From: MCAFEE, INC.
To: MCAFEE, LLC
Reel/Frame 043665/0918 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 14, 2006
From: DALCHER, GREGORY WILLIAM; ELLIOTT, SCOTT CLEMENTSON; LOWE, JOE C.
To: MCAFEE, INC.
Reel/Frame 017590/0549 →