A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6 , and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3 . Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.
1. A microprocessor comprising:
a first processing unit including an address generator;
a second processing unit;
first, second and third address buses coupled to the first processing unit;
first, second and third data buses coupled to the second processing unit, wherein the first data bus is coupled to the first processing unit;
a first memory coupled to the first address bus, second address bus, first data bus and second data bus;
a second memory coupled to the first address bus, third address buses, first data bus and third data bus;
wherein the address generator generates address signals to access the first memory and the second memory via the second and third address buses, in parallel.
2. The microprocessor according to claim 1 ,
wherein the address generator generates first, second and third address signals;
wherein the first processing unit receives first data via the first data bus corresponding to the first address signal,
wherein the first data includes an instruction, and
wherein the first processing unit executes the instruction, and the address generator generates a second address signal provided to the second address bus and a third address signal provided to the third address bus, in parallel.
3. The microprocessor according to claim 2 ,
wherein the second processing unit receives second data via the second data bus corresponding to the second address signal, and receives third data via the third data bus corresponding to the third address signal.
4. A microprocessor comprising:
a first processing unit including an address generator;
a second processing unit;
first, second and third address buses coupled to the first processing unit;
first, second and third data buses coupled to the second processing unit, wherein the first data bus is coupled to the first processing unit;
a first memory coupled to the first address bus, second address bus, first data bus and second data bus;
a second memory coupled to the first address bus, third address buses, first data bus and third data bus;
wherein the address generator generates an address signal to access either the first memory or the second memory via one of the first, second and third address buses,
wherein the address generator includes a first address generating unit and a second address generating unit,
wherein the first address generating unit generates the plurality of address signals which are output to the first address bus, and
wherein the second address generating unit generates a second address signal for output to the second address bus and a third address signal for output to the third address bus to access the first and second memories.
5. The microprocessor according to claim 4 ,
wherein the second processing unit receives second data corresponding to the second address signal and third data corresponding to the third address signal, in parallel.
6. The microprocessor according to claim 5 ,
wherein the second processing unit executes based on the second data from the second data bus and the third data from the third data bus.
7. The microprocessor according to claim 1 ,
wherein the first processing unit outputs a first address signal to the first address bus, and
wherein the first processing unit outputs the address signals to the second address bus and the third address bus, respectively.
8. The microprocessor according to claim 4 ,
wherein the second processing unit is operable to receive data signals from an arbitrary one of the first memory and second memory via the second and third data buses corresponding to the address signals from the first processing unit.
9. The microprocessor according to claim 5 ,
wherein the second processing unit includes an execution unit, and
wherein the execution unit performs operations using the second data and the third data.
10. The microprocessor according to claim 1 ,
wherein the first processing unit receives data signals from the first data bus corresponding to the address signals of the first address bus output from the address generator,
wherein the data signals from the first data bus include an instruction, and
wherein the first processing unit decodes and executes the instruction.
11. The microprocessor according to claim 4 , wherein the microprocessor is formed on a semiconductor integrated circuit.
12. A microprocessor comprising:
a first processing unit including an address generator;
a second processing unit;
first, second and third address buses coupled to the first processing unit;
first, second and third data buses coupled to the second processing unit;
a first memory coupled to the first address bus, second address bus, first data bus and second data bus;
a second memory coupled to the first address bus, third address bus, first data bus and third data bus,
wherein the first processing unit is coupled to the first data bus,
wherein the address generator generates a plurality of address signals output to the first, second and third address buses,
wherein the plurality of address signals include a second address signal output to the second address bus and a third address signal output to the third address bus to access the first memory and the second memory, in parallel.
13. The microprocessor according to claim 12 , wherein the second processing unit receives data from the second data bus and data from the third data bus, in parallel.