Method and apparatus for fabricating semiconductor chips using varying areas of precision
View Patent ↗A system that fabricates a semiconductor chip. The system places patterns for components which require fine line-widths within a high resolution region of a reticle, wherein the high resolution region provides sharp focus for a given wavelength of light used by the lithography system. At the same time, the system places patterns for components which do not require fine line-widths outside of the high-resolution region of the reticle, thereby utilizing the region outside of the high-resolution region of the reticle instead of avoiding the region. Note that the coarseness for components placed outside of the high resolution region of the reticle is increased to compensate for the loss of optical focus outside of the high resolution region.
1. A method for fabricating a semiconductor chip, comprising:
receiving a reticle which includes a pre-determined high-resolution region and a pre-determined region outside of the high-resolution region, wherein the high-resolution region provides sharp optical focus for a given wavelength of light used by a lithography system, and wherein the region outside of the high-resolution region provides a lower resolution of optical focus, and wherein the region outside of the high-resolution region surrounds a periphery of the high-resolution region;
placing patterns for components which require fine line-widths within the high-resolution region of the reticle;
placing patterns for components which do not require fine line-widths within the region outside of the high-resolution region of the reticle, thereby utilizing the region outside of the high-resolution region of the reticle instead of avoiding the region outside of the high-resolution region of the reticle;
wherein the coarseness for components placed within the region outside of the high-resolution region of the reticle is increased to compensate for the loss of optical focus outside of the high-resolution region.
2. The method of claim 1 , wherein placing the patterns for components which require fine line-widths involves placing patterns for dense, finely-patterned memory structures within the high-resolution region of the reticle.
3. The method of claim 1 , wherein placing the patterns for components which do not require fine line-widths involves placing patterns for coarse wires and coarse transistors outside of the high-resolution region of the reticle.
4. The method of claim 1 , wherein placing the patterns for components which do not require fine line-widths involves placing patterns for capacitively, inductively, or optically coupled terminals outside of the high-resolution region of the reticle.
5. The method of claim 1 , wherein the coarseness of patterns placed outside of the high-resolution region of the reticle increases by gradual changes in the minimum dimensions of transistors and wires as the patterns are placed further from the high-resolution region of the reticle.
6. The method of claim 1 , wherein the coarseness of patterns placed outside of the high-resolution region of the reticle increases by large focus-steps at the boundary between the high-resolution region of the reticle and the region outside of the high-resolution region of the reticle.
7. The method of claim 1 , further comprising:
creating multiple large reticles, which have a dense core within a high-resolution region, and which have coarse wires outside of the high-resolution region; and
imaging the large reticles across a wafer by stepping the reticles so that the coarse wires overlap and intersect, thereby obviating the need to use separate lithographic masks for the dense cores and for the coarse wires between the dense cores to create a wafer-scale integration chip.