Fast virtual to physical memory mapping
View Patent ↗A system and method for managing memory is disclosed. The system includes a computer memory array and a memory management unit accessible to the memory array. The memory management unit includes a plurality of parallel comparators. The comparators receive a virtual memory address and perform a comparison of the virtual memory address to a plurality of predetermined addresses. The memory management unit also includes logic responsive to outputs of each of the comparators to determine a physical memory address of an element within the memory array.
1. A memory device comprising:
a memory array; and
a memory management unit accessible to the memory array, the memory management unit including:
a plurality of parallel comparators to receive a portion of a virtual memory address, each comparator to perform a comparison of the portion of the virtual memory address to a portion of a predetermined address of a plurality of predetermined addresses, wherein the predetermined address for each comparator is stored in hardware in a plurality of logic gates with fixed inputs; and
logic responsive to outputs of each of the plurality of parallel comparators to determine a physical memory address of the memory array associated with the virtual memory address;
wherein the portion of the virtual memory address includes a middle portion and an upper portion, wherein a bus truncates the upper portion of the virtual address and each of the plurality of parallel comparators receive the middle portion and the truncated upper portion of the virtual address.
2. The memory device of claim 1 , wherein the responsive logic includes a multiplexer, and wherein at least two of the plurality of parallel comparators receive a common physical predetermined address.
3. The memory device of claim 1 , wherein an address space of virtual memory addresses comparable by the plurality of comparators is greater than a physical address space of the memory array.
4. The memory device of claim 3 , wherein the address space of the virtual memory addresses comparable by the plurality of comparators is more than ten times greater than the physical address space of the memory array.
5. The memory device of claim 1 , wherein the responsive logic sends a fault indication when the portion of the virtual memory address does not correspond to any one of the plurality of predetermined addresses.
6. The method of claim 1 , wherein the predetermined address is a physical address.
7. The method of claim 1 , wherein the memory array stores a frequently-used function of a software program.
8. The method claim 7 , wherein the frequently-used function is a music playback function.
9. A memory management unit, comprising:
a plurality of parallel comparators to receive a portion of a virtual memory address, each comparator to perform a comparison of the portion of the virtual memory address to a portion of a predetermined physical address of a plurality of predetermined physical addresses of a memory, wherein the predetermined physical address for each comparator is stored in a plurality of logic gates with fixed inputs; and
logic responsive to outputs of each of the plurality of parallel comparators to determine a physical memory address associated with the virtual memory address;
wherein the portion of the virtual memory address includes a middle portion and an upper portion, wherein a bus truncates the upper portion of the virtual memory address and each of the plurality of parallel comparators receive the middle portion and the truncated upper portion of the virtual address.
10. The memory management unit of claim 9 , further comprising:
a fault output responsive to the responsive logic, wherein the responsive logic asserts a signal at the fault output when the portion of the virtual memory address does not correspond to any of the predetermined physical addresses.
11. The memory management unit of claim 9 , wherein the portion of the virtual memory address is received from a direct memory access (DMA) device.
12. The memory management unit of claim 9 , wherein the memory management unit and a memory array are located together on an integrated circuit.
13. The memory management unit of claim 9 , wherein the logic includes a multiplexer.
14. The memory management unit of claim 9 , wherein the portion of the virtual memory address is received from a central processing unit (CPU).
15. A memory, comprising:
a plurality of addressable memory locations, wherein each memory location corresponds to a physical address;
an input to receive a physical address request corresponding to one of a physical address of one of the plurality of addressable memory locations; and
an output to provide data to a memory bus;
wherein the physical address request is received from a memory management unit that includes:
a bus configured to receive a portion of a virtual memory address;
a plurality of parallel comparators to receive the portion of the virtual memory address, each comparator to concurrently perform a comparison of the portion of the virtual memory address to a predetermined physical address associated with the comparator; and
logic responsive to outputs of each of the plurality of parallel comparators to determine a physical memory address of an element within a memory array; and
wherein the portion of the virtual memory address includes a middle portion and an upper portion, and wherein the bus is configured to receive the middle portion and to truncate the upper portion of the virtual address.
16. The method of claim 15 , wherein a lower portion of the virtual memory address is identical to a lower portion of an associated physical address.
17. The method of claim 16 , further comprising: providing the lower portion of the virtual memory address to the computer memory array.
18. A method of managing a memory device, the method comprising:
receiving a virtual address from a computer device at a memory management unit coupled to the memory device;
concurrently comparing a portion of the virtual address using a plurality of different comparators, each of the plurality of different comparators associated with a physical address of the memory device, wherein the virtual address includes a middle portion and an upper portion, and wherein the upper portion of the virtual memory address is truncated by a bus at the memory management unit;
determining a physical address to access the memory device after performing the concurrent comparison; and
wherein at least two of the different comparators are associated with a common physical address.
19. The method of claim 18 , wherein the memory management unit is coupled to the memory device.
20. The method of claim 19 , wherein the memory management unit is embedded within the memory device.
21. The method of claim 18 , wherein concurrently comparing at least a portion of the virtual address includes comparing a the middle portion of the virtual address.
22. The method of claim 18 , wherein the computer device is a direct memory access (DMA) device.
23. The method of claim 18 , wherein a lower portion of the virtual memory address is identical to a lower portion of a predetermined physical address associated with the virtual memory address.