Method of manufacturing semiconductor integrated circuit
View Patent ↗A method of manufacturing a semiconductor integrated circuit including a logic part and a memory array part, the logic part having N-type and P-type FETs, and the memory array part having N-type and P-type FETs, includes the steps of forming N-type and P-type FETs constituting the logic part and the memory array part, thereafter sequentially forming a first insulation film having a tensile stress and a second insulation film on the whole surface, selectively removing the second insulation film and the first insulation film present on the upper side of the region of the P-type FET constituting the logic part, then forming a third insulation film having a compressive stress on the whole surface, and thereafter selectively removing the third insulation film present on the upper side of the region of the N-type FET constituting the logic part and the third insulation film present on the upper side of the regions of the N-type and P-type FETs constituting the memory array part.
1. A method of manufacturing a semiconductor integrated circuit said method comprising the steps of:
(A) forming a logic part and a memory array part in a semiconductor substrate the logic part and the memory array part each including (1) an N channel type field effect transistor comprising gate parts, channel regions and source/drain regions, and (2) a P channel type field effect transistor comprising gate parts, channel regions and source/drain regions;
(B) forming a first insulation film having a tensile stress on an entire surface of the semiconductor substrate with said logic part and said memory array part formed therein and forming a second insulation film on said first insulation film;
(C) selectively removing said second insulation film and said first insulation film present on an upper side of a region of said P channel type field effect transistor in said logic part;
(D) forming a third insulation film having a compressive stress on a whole surface; and
(E) selectively removing said third insulation film present on an upper side of a region of said N channel type field effect transistor in said logic part and an upper side of a region of said N channel type field effect transistor in said memory array part and an upper side of a region of said P channel type field effect transistor in said memory array part;
(G) applying ion implantation for relaxation of tensile stress to said first insulation film on the region of said P channel type field effect transistor in said memory array subsequent to step (E).
2. The method of manufacturing a semiconductor integrated circuit as set forth in claim 1 , wherein said first insulation film and said third insulation film are each comprised of a silicon nitride film, and said second insulation film is comprised of a silicon oxide film.
3. A method of manufacturing a semiconductor integrated circuit said method comprising the steps of:
(A) forming a logic part and a memory array part in a semiconductor substrate each including (1) an N channel type field effect transistor comprising gate parts, channel regions and source/drain regions, and (2) a P channel type field effect transistor comprising gate parts, channel regions and source/drain regions;
(B) forming a first insulation film having a tensile stress on an entire surface of the semiconductor substrate with said logic part and said memory array part formed therein and forming a second insulation film on said first insulation film;
(C) selectively removing said second insulation film and said first insulation film present on an upper side of a region of said P channel type field effect transistor in said logic part;
(D) forming a third insulation film having a compressive stress on a whole surface;
(E) applying ion implantation for relaxation of compressive stress to said third insulation film present on an upper side of a region of said N channel field effect transistor in said memory array part and selectively removing said third insulation film present on an upper side of a region of said N channel type field effect transistor in said logic part; and
(F) applying ion implantation for relaxation of tensile stress to said first insulation film on a region of said P channel type field effect transistor in said memory array part at any point between steps (B)-(D).
4. The method of manufacturing a semiconductor integrated circuit as set forth in claim 3 , wherein said first insulation film and said third insulation film are each comprised of a silicon nitride film, and said second insulation film is comprised of a silicon oxide film.
5. A method of manufacturing a semiconductor integrated circuit, said method comprising the steps of:
(A) forming a logic part and a memory array part in a semiconductor substrate each including (1) an N channel type field effect transistor comprising gate parts, channel regions and source/drain regions, and (2) a P channel type field effect transistor comprising gate parts, channel regions and source/drain regions;
(B) forming a first insulation film having a tensile stress on an entire surface of the semiconductor substrate with said logic part and said memory array part formed therein and forming a second insulation film on said first insulation film;
(C) selectively removing said second insulation film present on an upper side of a region of said N channel type field effect transistor and said P channel type field effect transistor in said logic part;
(D) selectively removing said first insulation film present on said region of said P channel type field effect transistor constituting said logic part;
(E) forming a third insulation film having a compressive stress on a whole surface; and
(F) selectively removing said third insulation film present on the upper side of said region of said N channel type field effect transistor in said logic part and said third insulation film present on an upper side of a region of said N channel type field effect transistor and an upper side of a region of said P channel type field effect transistor in said memory array part;
(G) applying ion implantation for relaxation of tensile stress to said first insulation film on the region of said P channel type field effect transistor constituting said memory array subsequent to step (F).
6. The method of manufacturing a semiconductor integrated circuit as set forth in claim 5 , wherein said first insulation film and said third insulation film are each comprised of a silicon nitride film, and said second insulation film is comprised of a silicon oxide film.
7. A method of manufacturing a semiconductor integrated circuit said method comprising the steps of:
(A) forming a logic part and a memory part in a semiconductor substrate each including (1) an N channel type field effect transistor comprising gate parts, channel regions and source/drain regions, and (2) a P channel type field effect transistor comprising gate parts, channel regions and source/drain regions
(B) forming a first insulation film having a tensile stress on an entire surface of the semiconductor substrate with said logic part and said memory array part formed therein and forming a second insulation film on said first insulation film;
(C) selectively removing said second insulation film present on both an upper side of a region of said N channel type field effect transistor and an upper side of a region of said P channel type field effect transistor in said logic part;
(D) selectively removing said first insulation film present on the region of said P channel type field effect transistor constituting said logic part;
(E) forming a third insulation film having a compressive stress on a whole surface;
(F) applying ion implantation for relaxation of compressive stress to said third insulation film present on an upper side of a region of said N channel type field effect transistor in said memory array part, and selectively removing said third insulation film present on the upper side of the region of said N channel type field effect transistor constituting said logic part; and
(G) applying ion implantation for relaxation of tensile stress to said first insulation film on a region of said P channel type field effect transistor in said memory array part at any point between step (B) and step (D).
8. The method of manufacturing a semiconductor integrated circuit as set forth in claim 7 , wherein said first insulation film and said third insulation film are each comprised of a silicon nitride film, and said second insulation film is comprised of a silicon oxide film.