Semiconductor integrated circuit device
View Patent ↗A semiconductor integrated circuit device includes: a protected circuit protected against electro-static discharge applied from outside the device; an SCR protection circuit having an anode terminal connected to a power line, a cathode terminal connected to a ground line and a trigger terminal; and a trigger circuit connected to the trigger terminal and including an RC circuit connected between the power line and the ground line.
1. A semiconductor integrated circuit device comprising:
a protected circuit protected against electro-static discharge applied from outside the device;
an SCR protection circuit having:
a pnp bipolar transistor including an emitter connected to a power line and a collector connected to a trigger terminal;
an npn bipolar transistor including an emitter connected to a ground line, a collector connected to a base of the pnp bipolar transistor, and a base connected to the trigger terminal;
a first resistor having one terminal connected to the trigger terminal and the other terminal connected to the ground line; and
a second resistor having one terminal connected to the power line and the other terminal connected to the collector of the npn bipolar transistor; and
a trigger circuit connected to the trigger terminal and including an RC circuit connected between the power line and the ground line, the RC circuit having a fourth resistor and a capacitor; and
a third resistor having one terminal connected to the trigger terminal and the trigger circuit and the other terminal connected to the ground line,
wherein the trigger circuit includes:
a p-transistor having one terminal connected to the power line and another terminal connected to the trigger terminal and the one terminal of the third resistor;
a NAND gate having an output terminal connected to a gate of the p-transistor;
the capacitor having one terminal connected to the power line and another terminal connected to a first input terminal of the NAND gate;
the fourth resistor having one terminal connected to the first input terminal of the NAND gate and the other terminal connected to the ground line; and
an inverter having an input terminal connected to the trigger terminal and an output terminal connected to a second input terminal of the NAND gate.
2. A semiconductor integrated circuit device of comprising:
a protected circuit protected against electro-static discharge applied from outside the device;
an SCR protection circuit having:
a pnp bipolar transistor including an emitter connected to a power line and a collector connected to a trigger terminal;
an npn bipolar transistor including an emitter connected to a ground line, a collector connected to a base of the pnp bipolar transistor, and a base connected to the trigger terminal;
a first resistor having one terminal connected to the trigger terminal and the other terminal connected to the ground line; and
a second resistor having one terminal connected to the power line and the other terminal connected to the collector of the npn bipolar transistor; and
a trigger circuit connected to the trigger terminal and including an RC circuit connected between the power line and the ground line, the RC circuit having a fourth resistor and a capacitor; and
a third resistor having one terminal connected to the trigger terminal and the trigger circuit and the other terminal connected to the ground line, wherein the trigger circuit includes:
an n-transistor having one terminal connected to the power line and another terminal connected to the trigger terminal and the one terminal of the third resistor;
a NOR gate having an output terminal connected to a gate of the n-transistor;
the capacitor having one terminal connected to the ground line and another terminal connected to a first input terminal of the NOR gate; the fourth resistor having one terminal connected to the first input terminal of the NOR gate and the other terminal connected to the power line;
and a buffer having an input terminal connected to the trigger terminal and an output terminal connected to a second input terminal of the NOR gate.
3. A semiconductor integrated circuit device comprising:
a protected circuit protected against electro-static discharge applied from outside the device;
an SCR protection circuit having:
an npn bipolar transistor including an emitter connected to a ground line and a collector connected to a trigger terminal;
a pnp bipolar transistor including an emitter connected to a power line, a collector connected to a base of the npn bipolar transistor, and a base connected to the trigger terminal;
a first resistor having one terminal connected to the trigger terminal and the other terminal connected to the power line; and
a second resistor having one terminal connected to the ground line and the other terminal connected to the collector of the pnp bipolar transistor; and
a trigger circuit connected to the trigger terminal and including an RC circuit connected between the power line and the ground line, the RC circuit having a fourth resistor and a capacitor; and
a third resistor having one terminal connected to the trigger terminal and the trigger circuit and the other terminal connected to the power line,
wherein the trigger circuit includes:
a p-transistor having one terminal connected to the ground line and another terminal connected to the trigger terminal and the one terminal of the third resistor;
a NAND gate having an output terminal connected to a gate of the p-transistor;
the capacitor having one terminal connected to the power line and another terminal connected to a first input terminal of the NAND gate;
the fourth resistor having one terminal connected to the first input terminal of the NAND gate and the other terminal connected to the ground line; and a buffer having an input terminal connected to the trigger terminal and an output terminal connected to a second input terminal of the NAND gate.
4. A semiconductor integrated circuit device comprising:
a protected circuit protected against electro-static discharge applied from outside the device;
an SCR protection circuit having:
an npn bipolar transistor including an emitter connected to a ground line and a collector connected to a trigger terminal;
a pnp bipolar transistor including an emitter connected to a power line, a collector connected to a base of the npn bipolar transistor, and a base connected to the trigger terminal;
a first resistor having one terminal connected to the trigger terminal and the other terminal connected to the power line; and
a second resistor having one terminal connected to the ground line and the other terminal connected to the collector of the pnp bipolar transistor; and
a trigger circuit connected to the trigger terminal and including an RC circuit connected between the power line and the ground line, the RC circuit having a fourth resistor and a capacitor; and
a third resistor having one terminal connected to the trigger terminal and the trigger circuit and the other terminal connected to the power line,
wherein the trigger circuit includes:
an n-transistor having one terminal connected to the ground line and another terminal connected to the trigger terminal and the one terminal of the third resistor;
a NOR gate having an output terminal connected to a gate of the n-transistor;
the capacitor having one terminal connected to the ground line and another terminal connected to a first input terminal of the NOR gate;
the fourth resistor having one terminal connected to the first input terminal of the NOR gate and the other terminal connected to the power line; and
an inverter having an input terminal connected to the trigger terminal and an output terminal connected to a second input terminal of the NOR gate.
5. The device of claim 1 , comprising a pn diode connected in parallel with the protected circuit and having a cathode connected to the power line and an anode connected to the ground line.
6. The device of claim 1 , comprising an nMOS transistor connected in parallel with the protected circuit and having one terminal connected to the power line, another terminal connected to the ground line and a gate connected to the ground line via a fifth resistor.
7. The device of claim 1 , comprising a pMOS transistor connected in parallel with the protected circuit and having one terminal connected to the power line, another terminal connected to the ground line and a gate connected to the power line via a fifth resistor.
8. The device of claim 3 , comprising a pn diode connected in parallel with the protected circuit and having a cathode connected to the power line and an anode connected to the ground line.
9. The device of claim 3 , comprising an nMOS transistor connected in parallel with the protected circuit and having one terminal connected to the power line, another terminal connected to the ground line, and a gate connected to the ground line via a fifth resistor.
10. The device of claim 3 , comprising a pMOS transistor connected in parallel with the protected circuit and having one terminal connected to the power line, another terminal connected to the ground line, and a gate connected to the power line via a fifth resistor.
11. The device of claim 2 , comprising a pn diode connected in parallel with the protected circuit and having a cathode connected to the power line and an anode connected to the ground line.
12. The device of claim 2 , comprising an nMOS transistor connected in parallel with the protected circuit and having one terminal connected to the power line, another terminal connected to the ground line and a gate connected to the ground line via a fifth resistor.
13. The device of claim 2 , comprising a pMOS transistor connected in parallel with the protected circuit and having one terminal connected to the power line, another terminal connected to the ground line and a gate connected to the power line via a fifth resistor.
14. The device of claim 4 , comprising a pn diode connected in parallel with the protected circuit and having a cathode connected to the power line and an anode connected to the ground line.
15. The device of claim 4 , comprising an nMOS transistor connected in parallel with the protected circuit and having one terminal connected to the power line, another terminal connected to the ground line, and a gate connected to the ground line via a fifth resistor.
16. The device of claim 4 , comprising a pMOS transistor connected in parallel with the protected circuit and having one terminal connected to the power line, another terminal connected to the ground line, and a gate connected to the power line via a fifth resistor.