Triggered data generator
View Patent ↗A triggered data generator reduces timing jitter at the start of serial data output from arrival of a trigger signal. A trigger detecting circuit 8 produces trigger phase information indicating the phase relationship between the trigger signal and a reference clock. A data pattern generating circuit 10 generates parallel data bits according to the reference clock in response to the trigger signal. A data shifting circuit 11 rearranges the parallel data bits in a predetermined order to produce shifted parallel data bits in which data bit order is shifted relative to the reference clock as a function of the trigger phase information. A parallel to serial converter 16 converts the shifted parallel data bits into serial data bits.
1. A data generator producing serial data bits in response to a trigger signal comprising:
means for detecting a phase relationship between the trigger signal and a reference clock by generating phase-shifted clocks of the reference clock that are a function of a parallel data bit count, and sampling the trigger signal by the phase-shifted clocks to produce a clock synchronized trigger signal and trigger phase information;
means for generating the parallel data bits according to the clock synchronized trigger;
means for shifting the parallel data bits in a predetermined order relative to the reference clock according to the trigger phase information to produce shifted parallel data bits; and
means for converting the shifted parallel data bits into serial data bits.
2. The data generator recited in claim 1 wherein the data shifting means has means for delaying a selected number of bits of the parallel data bits by one clock of the reference clock and combining bits by the current reference clock and the bits delayed by one clock of the reference clock to produce the shifted parallel data bits as a function of the trigger phase information.
3. The data generator recited in claim 2 wherein the data shifting means has means for selecting the bits by the current reference clock and the bits delayed by one clock of the reference clock to produce the shifted parallel data bits in which the bits by the current reference clock and the bits delayed by one clock of the reference clock data are rearranged in the predetermined order as a function of the trigger phase information.
4. The data generator recited in claim 1 wherein the serial data bits are produced in response to a clock having a frequency that is a function of the number of the parallel data bits.
5. A method of generating serial data bits in response to a trigger signal comprising the steps of:
detecting a phase relationship between the trigger signal and a reference clock by sampling the trigger signal using phase-shifted clocks of the reference clock that are a function of a parallel data bit count to produce a clock synchronized trigger and trigger phase information;
generating the parallel data bits according to the clock synchronized trigger;
shifting the bits of the parallel data bits in the predetermined order as a function of the trigger phase information to produce shifted parallel data bits relative to the reference clock; and
converting the shifted parallel data bits into serial data bits.
6. The method for generating serial data bits recited in claim 5 wherein the shifting step further comprises the step of delaying a selected number of bits of the parallel data bits by one clock of the reference clock and combining bits by the current reference clock and the bits delayed by one clock of the reference clock to produce the shifted parallel data bits as a function of the trigger phase information.
7. The method for generating serial data bits recited in claim 6 wherein the combining step further comprises rearranging the parallel data bits in the predetermined order by selecting bits by the current reference clock and the bits delayed by one clock of the reference clock as a function of the trigger phase information.
8. The method for generating serial data bits recited in claim 5 wherein the serial data bits are generated in response to a clock having a frequency that is a function of the number of the parallel data bits.