Contact portion of semiconductor device, and thin film transistor array panel for display device including the contact portion

1. A method for manufacturing a semiconductor device comprising:

forming first wire on a substrate;

forming a lower film on the first wire;

forming a photosensitive pattern on the lower film using a photosensitive material;

forming contact holes for exposing the first wire by etching the lower film using the photosensitive film as an etching mask;

removing part of the photosensitive film pattern by an ashing process to expose a borderline of the lower film defining the contact holes; and

forming second wire connected to the first wire via the contact holes.

2. The method of claim 1 , wherein the lower film is formed of an insulating film made of SiNx or SiOx.

3. The method of claim 1 , wherein the lower film is formed of a conducting film.

4. The method of claim 1 , comprising:

forming the lower film of a first insulating film and a second insulating film;

exposing the borderline of the lower film; and

thereafter, etching the second insulating film not blocked by the photosensitive film pattern to expose the borderline of the first insulating film in the contact holes.

5. The method of claim 1 , wherein the photosensitive film pattern around the contact holes is formed thinner than that in the other portions.

6. A method for manufacturing a thin film transistor array panel for liquid crystal display comprising:

forming gate wire including a gate line, a gate electrode connected to the gate line, and a gate pad connected to one end of the gate line;

depositing a gate insulating film;

forming a semiconductor layer;

forming data wire including a data line crossing with the gate line, a source electrode connected to the data electrode and adjacent to the gate electrode, a drain electrode placed opposite to the source electrode in relation to the gate electrode, and a data pad connected to one end of the date line;

depositing an insulating film;

forming a photosensitive organic insulating film pattern on the insulating film;

etching the insulating film using the organic insulating film pattern as an etching mask to expose first contact holes for exposing the gate pad or the data pad;

performing an ashing process to expose borderline of the insulating film in the contact holes; and

forming an assistant pad connected to the gate pad or the data pad via the first contact holes.

7. The method of claim 6 , wherein the organic insulating film pattern around the contact holes is formed thinner than that in the other portions.

8. The method of claim 7 , further comprising:

forming the insulating film of a first insulating film and a second insulating film;

exposing the borderline of the insulating film;

thereafter, etching the second insulating film not blocked by the organic insulating pattern; and

removing the organic insulating pattern.

9. The method of claim 8 , wherein the second insulating film is a low dielectric insulating film which has a low dielectric constant less than 4.0 and is formed by a chemical vapor deposition.

10. The method of claim 6 , wherein the organic insulating film pattern has second contact holes for exposing the drain electrode with the insulating film,

further comprising forming a pixel electrode electrically connected to the drain electrode via the second contact holes on the same layer as the assistant pad.

11. The method of claim 10 , wherein the second contact holes are formed with the first contact holes, and the organic insulating pattern around the contact holes is formed thinner than that in the other portions.

12. The method of claim 6 , wherein the thin film transistor array panel for liquid crystal display has a portion where a seal line for sealing a liquid crystal material is formed,

further comprising:

forming the organic insulating film pattern at the portion thinner than that at the other portions; and

removing the organic insulating film pattern at the portion by the ashing process.

13. The method of claim 6 , wherein both the data wire and the semiconductor layer are formed by a photo etching process using photosensitive patterns whose thickness is partly different.