High voltage GaN-based transistor structure
View Patent ↗The present invention relates to a high voltage and high power gallium nitride (GaN) transistor structure. In general, the GaN transistor structure includes a sub-buffer layer that serves to prevent injection of electrons into a substrate during high voltage operation, thereby improving performance of the GaN transistor structure during high voltage operation. Preferably, the sub-buffer layer is aluminum nitride, and the GaN transistor structure further includes a transitional layer, a GaN buffer layer, and an aluminum gallium nitride Schottky layer.
1. A method of fabricating a high voltage gallium nitride (GaN) transistor structure comprising:
a) depositing a plurality of structural epitaxial layers on a substrate, comprising:
i) depositing a transitional layer above the substrate;
ii) depositing an aluminum nitride sub-buffer layer above the transitional layer, the sub-buffer layer adapted to increase a source-drain breakdown voltage of the GaN transistor structure by preventing electrons from entering the transitional layer and the substrate during high voltage operation; and
iii) depositing a GaN buffer layer above the sub-buffer layer; and
b) forming electrical contacts on the plurality of structural epitaxial layers, thereby forming a high electron mobility transistor.
2. The method of claim 1 wherein the depositing the plurality of structural epitaxial layers step further comprises depositing a Schottky layer above the GaN buffer layer.
3. The method of claim 2 wherein the Schottky layer is essentially aluminum gallium nitride.
4. The method of claim 2 wherein the depositing the plurality of structural epitaxial layers step further comprises depositing a GaN termination layer above the Schottky layer, the GaN termination layer protecting the Schottky layer from surface reactions.
5. The method of claim 4 wherein the GaN termination layer is further a reproducible termination layer, thereby increasing effectiveness of passivation.
6. The method of claim 4 wherein the GaN termination layer is sufficiently thin to allow electrons to tunnel through the GaN termination layer.
7. The method of claim 6 wherein the GaN termination layer is approximately 1-2 nanometers (nm) thick.
8. The method of claim 1 wherein the forming electrical contacts step comprises forming a source contact, a gate contact, and a drain contact.
9. The method of claim 1 wherein the sub-buffer layer is essentially aluminum nitride.
10. The method of claim 1 wherein a source-drain breakdown voltage is at least one-hundred (100) volts.
11. The method of claim 1 wherein the transitional layer is deposited on the substrate, the sub-buffer layer is deposited on the transitional layer, and the GaN buffer layer is deposited on the sub-buffer layer.