Method of fabricating semiconductor devices employing at least one modulation doped quantum well structure and one or more etch stop layers for accurate contact formation
View Patent ↗A method of fabricating a semiconductor device includes the steps of forming (or providing) a series of layers formed on a substrate, the layers including a first plurality of layers including an n-type ohmic contact layer, a p-type modulation doped quantum well structure, an n-type modulation doped quantum well structure, and a fourth plurality of layers including a p-type ohmic contact layer. Etch stop layers are used during etching operations when forming contacts to the n-type ohmic contact layer and contacts to the n-type modulation doped quantum well. Preferably, each such etch stop layer is made sufficiently thin to permit current tunneling therethrough during operation of optoelectronic/electronic devices realized from this structure (including heterojunction thyristor devices, n-channel HFET devices, p-channel HFET devices, p-type quantum-well-base bipolar transistor devices, and n-type quantum-well-base bipolar transistor devices). The etch stop layer(s) preferably comprise AlAs that functions as an etch stop during etching by a chlorine-based gas mixture that includes fluorine. The series of layers preferably comprise group III-V materials.
1. A method of fabricating a semiconductor device comprising the steps of:
providing a series of layers formed on a substrate, said layers including a first plurality of layers comprising n-type dopant material, a second plurality of layers that form a p-type modulation doped quantum well structure, and a third plurality of layers including at least one layer comprising n-type dopant material, wherein said first plurality of layers includes an n-type ohmic contact layer and a first etch stop layer formed above said n-type ohmic contact layer for contacting said n-type ohmic contact layer;
performing an etching operation that automatically stops at said first etch stop layer;
removing remaining portions of said first etch stop layer to expose first areas of said n-type ohmic contact layer;
depositing a first metal layer on said first areas of said n-type ohmic contact layer to form a gate terminal electrode of a first-type transistor device; and
depositing a second metal layer that is electrically coupled to said p-type modulation doped quantum well structure to form a source terminal electrode and a drain terminal electrode of said first-type transistor device.
2. A method of fabricating a semiconductor device according to claim 1 , further comprising the steps of:
performing a first implant of p-type ions to form at least one p-type implant region that is electrically coupled to said p-type modulation doped quantum well structure; and
depositing said second metal layer on said at least one p-type implant region.
3. A method of fabricating a semiconductor device according to claim 1 , further comprising the step of:
depositing a third metal layer that is operably coupled to said third plurality of layers to form a collector terminal electrode of said first-type transistor device.
4. A method of fabricating a semiconductor device according to claim 3 , further comprising the steps of:
performing a second implant of n-type ions to form an n-type implant region that is electrically coupled to said third plurality of layers, and
depositing said third metal layer on said n-type implant region.
5. A method of fabricating a semiconductor device according to claim 3 , wherein:
said third metal layer is deposited prior to said first and second metal layers.
6. A method of fabricating a semiconductor device according to claim 1 , further comprising the steps of:
providing said series of layers with a fourth plurality of layers comprising p-type dopant material and a p-type ohmic contact layer, wherein said third plurality of layers forms an n-type modulation doped quantum well structure; and
depositing a second metal layer that is electrically coupled to said n-type modulation doped quantum well structure to form a source terminal electrode and a drain terminal electrode of a second-type transistor device; and
depositing a third metal layer that is electrically coupled to said p-type ohmic contact layer to form a gate terminal electrode of said second-type transistor device.
7. A method of fabricating a semiconductor device according to claim 6 , further comprising the steps of:
performing a first implant of n-type ions to form at least one n-type implant region that is electrically coupled to said n-type modulation doped quantum well structure; and
depositing said second metal layer on said at least one n-type implant region.
8. A method of fabricating a semiconductor device according to claim 6 , further comprising the step of:
depositing a fourth metal layer that is operably coupled to said p-type modulation doped quantum well structure to form a collector terminal electrode of said second-type transistor device.
9. A method of fabricating a semiconductor device according to claim 8 , further comprising the steps of:
performing a second implant of p-type ions to form at least one p-type implant region that is electrically coupled to said p-type modulation doped quantum well structure, and
depositing said fourth metal layer on said at least one p-type implant region.
10. A method of fabricating a semiconductor device according to claim 9 , wherein:
said third metal layer is deposited prior to said second and fourth metal layers.
11. A method of fabricating a semiconductor device comprising the steps of:
providing a series of layers formed on a substrate, said layers including a first plurality of layers including at least one layer comprising p-type dopant material, a second plurality of layers that form an n-type modulation doped quantum well structure, and a third plurality of layers including at least one layer comprising p-type dopant material, wherein said third plurality of layers includes a p-type ohmic contact layer and a first etch stop layer formed above said n-type modulation doped quantum well structure for contacting said n-type modulation doped quantum well structure;
depositing a first metal layer on said p-type ohmic contact layer to form a gate terminal electrode of a first-type transistor device;
performing an etching operation that automatically stops at said first etch stop layer;
removing remaining portions of said first etch stop layer to expose first areas of a layer thereunder; and
depositing a second metal layer on said first areas to form a source terminal electrode and a drain terminal electrode of said first-type transistor device, wherein said source terminal electrode and said drain terminal electrode are electrically coupled to said n-type modulation doped quantum well structure.
12. A method of fabricating a semiconductor device according to claim 11 , wherein:
said first etch stop layer permits current tunneling.
13. A method of fabricating a semiconductor device according to claim 11 , further comprising the steps of:
performing a first implant of n-type ions in said first areas to form at least one n-type implant region that is electrically coupled to said n-type modulation doped quantum well structure; and
depositing said second metal layer on said at least one n-type implant region.
14. A method of fabricating a semiconductor device according to claim 11 , wherein:
said first plurality of layers forms a p-type modulation doped quantum well structure.
15. A method of fabricating a semiconductor device according to claim 14 , wherein:
said series of layers further comprises
a first plurality of undoped spacer layers disposed between said first plurality of layers and said second plurality of layers, and
a second plurality of undoped spacer layers disposed between said second plurality of layers and said third plurality of layers,
wherein said second plurality of undoped spacer layers include a thin capping layer.
16. A method of fabricating a semiconductor device according to claim 15 , further comprising the steps of:
performing an etching operation that exposes second areas between said n-type modulation doped structure and said p-type modulation doped structure;
depositing a third metal layer on said second areas to form a collector electrode of said first-type transistor device, wherein said collector electrode is electrically coupled to said p-type modulation doped quantum well structure.
17. A method of fabricating a semiconductor device according to claim 16 , further comprising the steps of:
performing a second implant of p-type ions in said second areas to form at least one p-type implant region that is electrically coupled to said p-type modulation doped quantum well structure; and
depositing said third metal layer on said at least one p-type implant region.