Method and system for testing a random access memory (RAM) device having an internal cache
A method for testing an internal bus of a random access memory (“RAM”) device, the RAM device having an internal cache coupled to a memory array by the internal bus, the method comprising: writing a value to an address in the RAM device, the value being stored in the internal cache, the value corresponding to at least one line of an external bus; writing a number of additional values to addresses in the RAM device other than the address to push the value from the internal cache into the memory array; reading a value from the address; and, determining whether the internal bus is faulty by comparing the value written to the value read.
1. A method for testing an internal bus of a random access memory (“RAM”) device, the RAM device having an internal cache coupled to a memory array by the internal bus, and the RAM device coupled to an external bus that provides data from a plurality of addresses to both the internal cache and the memory array, the method comprising the following steps:
writing a first value to a first address in the RAM device, the first value being stored in the internal cache, the first value corresponding to at least one line of the external bus;
writing a number of additional values to addresses in the RAM device other than the first address to fill the internal cache and thereby push the first value from the internal cache into the first address in the memory array;
reading a second value from the first address of the memory array;
determining whether the internal bus is faulty by comparing the first value written to the internal cache to the second value read from the memory array; and
reporting an error when the first value is not equal to the second value.
2. The method of claim 1 , further comprising the following step:
repeating the writing of the first value for each line of the external bus.
3. The method of claim 2 ,
wherein the external bus is a data bus and the first value written to the first address in the RAM device is equal to binary 1, and is incremented by a left shift for each line of the data bus, for determining whether said line is stuck high, stuck low, or shorted.
4. The method of claim 2 ,
wherein the external bus is an address bus and the first value written to the first address in the RAM device is a pattern for determining whether lines of the address bus are at least one of stuck high, stuck low, and shorted.
5. The method of claim 4 ,
wherein the first value written to the first address in the RAM device is an antipattern being the inverse of the pattern.
6. The method of claim 1 ,
wherein the number of additional values corresponds to a size of the internal cache.
7. The method of claim 1 ,
wherein the RAM device is a dynamic RAM (“DRAM”) device.
8. The method of claim 1 ,
wherein the RAM device is a static RAM (“SRAM”) device.
9. The method of claim 1 ,
wherein the cache is a SRAM device and the memory array is a DRAM device.
10. The method of claim 1 ,
wherein the RAM device is installed in a printed circuit board (“PCB”).
11. A system for testing an internal bus of a random access memory (“RAM”) device, the RAM device having an internal cache coupled to a memory array by the internal bus and the RAM device coupled to an external bus that provides data from a plurality of addresses to both the internal cache and the memory array, the system comprising:
a processor coupled to the RAM device through an interface; and
a program executed by the processor, the program including:
a module for writing a first value to a first address in the RAM device, the first value being stored in the internal cache, the first value corresponding to at least one line of the external bus;
a module for writing a number of additional values to addresses in the RAM device other than the first address to fill the internal cache and thereby push the first value from the internal cache into the first address in the memory array;
a module for reading a second value from the first address of the memory array;
a module for determining whether the internal bus is faulty by comparing the first value written to the internal cache to the second value read from the memory array; and
a module that reports an error when the first value is not equal to the second value.
12. The system of claim 11 and further comprising:
a module for repeating the writing of the first value for each line of the external bus.
13. The system of claim 12 ,
wherein the external bus is a data bus and the first value written to the first address in the RAM device is equal to binary 1, and is incremented by a left shift for each line of the data bus, for determining whether said line is stuck high, stuck low, or shorted.
14. The system of claim 12 ,
wherein the external bus is an address bus and the first value written to the first address in the RAM device is a pattern for determining whether lines of the address bus are at least one of stuck high, stuck low, and shorted.
15. The system of claim 14 ,
wherein the first value written to the first address in the RAM device is an antipattern being the inverse of the pattern.
16. The system of claim 11 ,
wherein the number of additional values corresponds to a size of the internal cache.
17. The system of claim 11 ,
wherein the RAM device is a dynamic RAM (“DRAM”) device.
18. The system of claim 11 ,
wherein the RAM device is a static RAM (“SRAM”) device.
19. The system of claim 11 ,
wherein the cache is a SRAM device and the memory array is a DRAM device.
20. The system of claim 11 ,
wherein the RAM device is installed in a printed circuit board (“PCB”).