Delay management circuit for reading out large S/H arrays
View Patent ↗An image sensor includes a plurality of pixels for capturing an image; a sample and hold circuit array having a plurality of units for receiving signals from the plurality of pixels representing the captured image; a decoder for selecting each of the units of the sample and hold circuit array for output; and a delay circuit that includes an adjustable time delay to the decoder for compensating for time delays.
1. An image sensor comprising:
(a) a plurality of pixels for capturing an image;
(b) a sample and hold circuit array having a plurality of units for receiving signals from the plurality of pixels representing the captured image;
(c) a delay circuit that includes an adjustable time delay for receiving address signals and, based on a particular address signal, generating a respective time delay for that address signal; and
(d) a decoder for receiving the delayed address signals and, based on each address signal, selecting a respective unit of the sample and hold circuit array for output.
2. The image sensor as in claim 1 , wherein the decoder includes a plurality of sequentially numbered unit addresses from 1 to N, and wherein the adjustable time delay decreases with an increase in unit address.
3. The image sensor as in claim 1 , wherein the adjustable delay circuit includes a plurality of delay cells and a multiplexer for selecting one or more of the delay cells according to the decoder address.
4. The image sensor as in claim 1 , wherein the delay circuit is a programmable delay circuit.
5. The image sensor as in claim 1 further comprising a synchronizer for synchronizing an output of the delay circuit and address inputs to the decoder.
6. A camera comprising:
an image sensor comprising:
(a) a plurality of pixels for capturing an image;
(b) a sample and hold circuit array having a plurality of units for receiving signals from the plurality of pixels representing the captured image;
(c) a delay circuit that includes an adjustable time delay for receiving address signals and, based on a particular address signal, generating a respective time delay for that address signal; and
(d) a decoder for receiving the delayed address signals and, based on each address signal, selecting a respective unit of the sample and hold circuit array for output.
7. The camera as in claim 6 , wherein the decoder includes a plurality of sequentially numbered unit addresses from 1 to N, and wherein the adjustable time delay decreases with an increase in unit address.
8. The camera as in claim 6 , wherein the adjustable delay circuit includes a plurality of delay cells and a multiplexer for selecting one or more of the delay cells according to the decoder address.
9. The camera as in claim 6 , wherein the delay circuit is a programmable delay circuit.
10. The camera as in claim 6 further comprising a synchronizer for synchronizing an output of the delay circuit and address inputs to the decoder.