Hardware-error tolerant computing
View Patent ↗Embodiments include a computing system, a device, and a method. A computing system includes a processor subsystem having an adjustable operating parameter. The computing system also includes an information store operable to save a sequence of instructions. The computing system further includes a controller module. The controller module includes a monitor circuit for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem. The controller further includes a control circuit for adjusting the adjustable operating parameter based upon an error-tolerant performance criterion.
1. A computing system comprising:
a processor subsystem having an adjustable operating parameter;
an information store operable to save a sequence of instructions; and
a controller module including:
a monitor circuit for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem; and
a control circuit for adjusting the adjustable operating parameter in substantial conformity with an error-tolerant performance criterion that corresponds to 0 =(Δ time to complete an execution of the sequence of instructions) divided by (Δ adjustable operating parameter).
2. A computing system comprising:
a processor subsystem having an adjustable operating parameter; an information store operable to save a sequence of instructions; and
a controller module including:
a monitor circuit for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem; and
a control circuit for adjusting a processor clock frequency in substantial conformity with 0 =(Δ time to complete an execution of the sequence of instructions) divided by (Δ processor clock frequency).
3. A computing system comprising:
a processor subsystem having an adjustable operating parameter;
an information store operable to save a sequence of instructions; and
a controller module including:
monitor circuit for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem; and
a control circuit for adjusting a processor clock frequency in substantial conformity with ±0.05 =(Δ time to complete an execution of the sequence of instructions) divided by (Δ processor clock frequency).
4. A computing system comprising:
a processor subsystem having an adjustable operating parameter;
an information store operable to save a sequence of instructions; and
a controller module including:
a monitor circuit for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem; and
a control circuit for adjusting a processor clock frequency in substantial conformity with ±0.10 =(Δ time to complete an execution of the sequence of instructions) divided by (Δ processor clock frequency).
5. A computing system comprising:
a processor subsystem having an adjustable operating parameter;
an information store operable to save a sequence of instructions; and
a controller module including:
a monitor circuit for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem; and
a control circuit for adjusting a processor clock frequency in substantial conformity with ±0.20 =(Δ time to complete an execution of the sequence of instructions) divided by (Δ processor clock frequency).
6. A computing system comprising:
a processor subsystem having an adjustable operating parameter;
an information store operable to save a sequence of instructions; and
a controller module including;
a monitor circuit for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem; and a control circuit for adjusting a processor voltage to substantially minimize
a time to complete an execution of the sequence of instructions.
7. A computing system comprising:
a processor subsystem having an adjustable operating parameter;
an information store operable to save a sequence of instructions; and
a controller module including;
a monitor circuit for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem; and
a control circuit for adjusting a processor clock frequency in substantial conformity with
0 =(Δ time to complete an execution of the sequence of instructions) divided by (Δ processor voltage).
8. A method implemented in a computerized system, the method comprising:
detecting an incidence of a processor-operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by a processor subsystem having an adjustable operating parameter; and
changing at least one of a voltage of the processor subsystem and/or a processor clock frequency based upon an error-tolerant performance criterion to substantially minimize a time required to successfully complete an execution of the sequence of instructions.
9. A method implemented in a computerized system, the method comprising:
detecting an incidence of a processor-operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by a processor subsystem having an adjustable operating parameter; and
changing a processor clock frequency in substantial conformity with 0 =(Δ time to complete an execution of the sequence of instructions) divided by (Δ processor clock frequency).
10. A method implemented in a computerized system, the method comprising:
detecting an incidence of a processor-operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by a processor subsystem having an adjustable operating parameter; and
changing a processor clock frequency in substantial conformity with 0 =(Δ time to complete an execution of the sequence of instructions) divided by (Δ processor voltage).