Data switch, and communication system using the data switch
View Patent ↗A preferred embodiment comprising a data switch includes a first processor for routing data packets including a MAC address, using a MAC address table stored in a writable memory. The switch further includes a second processor for routing data packets including an IP address using an IP address look-up table stored in the writable memory. The writable memory consists of a single memory fabric that is allocated between the MAC address table and the look-up table by a memory control unit according to a setting stored in a non-erasable memory unit.
1. A data switch for switching packets including a header that includes at least one of a MAC address and an IP address, the switch comprising:
a writable memory unit;
a MAC address switching unit for using a MAC address table stored in the writable memory unit to obtain switching information based on the MAC address in the header of a packet;
an IP address switching unit for using an IP address look-up table stored in the writable memory unit to obtain switching information based on the IP address in the header of a packet; and
a memory control unit for controlling allocation of writable memory between the IP address look-up table and the MAC address table, wherein controlling the allocation comprises controlling respective sizes of the IP address look-up table and the MAC address table based upon an application of the data switch.
2. The data switch according to claim 1 , wherein the memory control unit comprises a control memory storing at least one parameter for controlling the allocation of the writable memory unit between the IP address look-up table and the MAC address table.
3. The data switch according to claim 2 , wherein the control memory is arranged to store the at least one parameter without modification during operation of the data switch.
4. The data switch according to claim 1 , wherein the memory control unit receives read/write instructions from the MAC address switching unit and the IP address switching unit, derives from them a corresponding location in the writable memory unit, and implements the instructions in those locations.
5. The data switch according to claim 4 , wherein the memory control unit derives the corresponding location in the writable memory unit based on an address contained in the read/write instructions, the location depending on the size of the IP address lookup-table and the MAC address table.
6. A data switch comprising:
a writable memory unit;
a MAC address switching unit for using a MAC address table stored in the writable memory unit to obtain switching information based on a MAC address in a header of a packet;
an IP address switching unit for using an IP address look-up table stored in the writable memory unit to obtain switching information based on an IP address in the header of a packet;
a memory control unit for controlling allocation of writable memory between the IP address look-up table and the MAC address table and wherein controlling the allocation comprises
controlling respective sizes of the IP address look-up table and the MAC address table based upon an application of the data switch; and
controlling based upon at least one parameter selected from the group consisting of 1) a maximum number of MAC addresses, 2) a maximum number of IP addresses, 3) a minimum number of MAC addresses, 4) a minimum numbers of IP addresses, 5) a number of cycles for IP processing, 6) a number of buckets for MAC look-up, and 7) a width of a bucket in the MAC addresses table; and
an output unit arranged to receive the switching information from the MAC address switching unit and the IP address switching unit.
7. The data switch according to claim 6 , wherein when, from a given data packet, both the IP address switching unit and the MAC address switching unit generate switching information, the output unit operates according to the switching information generated by the IP address switching unit.
8. The data switch according to claim 6 , wherein when, from a given data packet, only one of the IP address switching unit and the MAC address switching unit generates switching information, the output unit transmits the switching information.
9. The data switch according to claim 6 , further comprising:
when, from a given data packet, both the IP address switching unit and the MAC address switching unit generate switching information, the output unit operates according to the switching information generated by the IP address switching unit; and
when, from a given data packet, only one of the IP address switching unit and the MAC address switching unit generates switching information, the output unit transmits the switching information.
10. The data switch according to claim 6 , wherein the memory control unit comprises a control memory storing the at least one parameter for controlling the allocation of the writable memory between the IP address look-up table and the MAC address table.
11. The data switch according to claim 10 , wherein the control memory is arranged to store the at least one parameter without modification during operation of the data switch.
12. The data switch according to claim 6 , wherein the memory control unit receives read/write instructions from the MAC address switching unit and the IP address switching unit, derives from them a corresponding location in the writable memory unit, and implements the instructions in those locations.
13. The data switch according to claim 12 , wherein the memory control unit derives the corresponding location in the writable memory unit based on an address contained in the read/write instructions, the location depending on the size of the IP address look-up table and the MAC address table.
14. A communication system comprising:
a data switch comprising:
a writable memory unit;
a MAC address switching unit for using a MAC address table stored in the writable memory unit to obtain switching information based on a MAC address in a header of a packet;
an IP address switching unit for using an IP address look-up table stored in the writable memory unit to obtain switching information based on an IP address in the header of a packet; and
a memory control unit for controlling allocation of writable memory between the IP address look-up table and the MAC address table, wherein controlling the allocation comprises controlling respective sizes of the IP address look-up table and the MAC address table based upon an application of the data switch;
a plurality of computer systems connected to the data switch by a local area network; and
a connection for connecting the data switch to the Internet.
15. The communication system according to claim 14 , wherein when, from a given data packet, both the IP address switching unit and the MAC address switching unit generate switching information, an output unit operates according to the switching information generated by the IP address switching unit.
16. The communication system according to claim 14 , wherein when, from a given data packet, only one of the IP address switching unit and the MAC address switching unit generates switching information, an output unit transmits the switching information.
17. The communication system according to claim 14 , wherein the memory control unit comprises a control memory storing at least one parameter for controlling the allocation of the writable memory between the IP address look-up table and the MAC address table.
18. The communication system according to claim 17 , wherein the control memory is arranged to store the at least one parameter without modification during operation of the data switch.
19. The communication system according to claim 14 , wherein the memory control unit receives read/write instructions from the MAC address switching unit and the IP address switching unit, derives from them a corresponding location in the writable memory unit, and implements the instructions in those locations.
20. The communication system according to claim 19 , wherein the memory control unit derives the corresponding location in the writable memory unit based on an address contained in the read/write instructions, the location depending on the size of the IP address look-up table and the MAC address table.
21. The data switch according to claim 1 , wherein controlling the allocation comprises controlling based upon 1) a maximum number of MAC addresses, 2) a maximum number of IP addresses, 3) a minimum number of MAC addresses, 4) a minimum numbers of IP addresses, 5) a number of cycles for IP processing, 6) a number of buckets for MAC look-up, and 7) a width of a bucket in the MAC address table.
22. The data switch according to claim 6 , wherein the at least one parameter comprises all of 1) the maximum number of MAC addresses, 2) the maximum number of IP addresses, 3) the minimum number of MAC addresses, 4) the minimum numbers of IP addresses, 5) the number of cycles for IP processing, 6) the number of buckets for MAC, and 7) the width of the bucket in the MAC table.