Receiver scheme for synchronous digital transmission
View Patent ↗A method, apparatus and system for improving the tolerance for timing jitter noise by eliminating the need to recover clock information from the input signal. There is no need to communicate clock synchronization information between transmit and receive gateways. In addition, the new receiving scheme can work in burst mode in its true sense, i.e., recovering data bits from the first incoming bit after an arbitrary period of time without transmitting.
1. A digital receiver for receiving digital information transmitted in an input pulse train, comprising:
a counter for providing a sequence of time stamps to a sample and hold circuit;
the sample and hold circuit for sequentially holding a time stamp from the sequence of time stamps, wherein each pulse from the input pulse train allows the corresponding time stamp to be stored in a buffer; and
a processor for determining the digital information by analyzing the time stamps stored in the buffer wherein the controller determines the binary value of a time slot by the time stamp and the digital transmission rate.
2. The receiver of claim 1 , further comprising a local clock communicably coupled to the counter.
3. The receiver of claim 1 , wherein the buffer comprises a first-in-first-out (FIFO) buffer for receiving time stamps from said counter and propagating said time stamps in response to said input pulse train.
4. The receiver of claim 2 , wherein the buffer includes shift registers that are triggered by the pulse train.
5. The receiver of claim 1 , further comprising optical logic gates adapted to process an optical pulse train.
6. The receiver of claim 1 , further comprising electrical logic gates adapted to process an electrical pulse train.
7. The method of claim 6 , wherein each time slot includes a time slot number N which is determined by N=t n /T, where t n is the arrival time of the n th pulse and 1/T is the digital transmission rate.
8. A method for recovering data from a sequence of received pulses, comprising:
recording the arrival times of at least two pulses within said sequence of received pulses, including storing the arrival time of each pulse of the sequence in a buffer;
determining from the arrival times a temporal relationship of the at least two pulses; and
assigning a binary value to a time slot determined by the temporal relationship of the pulses.
9. The method of claim 8 , wherein the determining and assigning steps further comprises:
extracting from the buffer a first arrival time associated with the first of the at least two pulses;
determining a first time slot number using the first arrival time;
assigning a logical “1” to the time slot associated with the first time slot number;
extracting from the buffer a second arrival time associated with the second of the at least two pulses;
determining a second time slot number using the second arrival time;
assigning a logical “1” to the time slot associated with a second time slot number; and
assigning a logical “0” to each time slot temporally positioned between the first and second time slots, the time slots having been assigned a logical “1” representing time slots associated with a valid input pulse.
10. The method of claim 8 , wherein each time slot includes a time slot number N which is determined by N=t n /T, where t n is the arrival time of the n th pulse and 1/T is the digital transmission rate.
11. The method of claim 8 , wherein the received input pulse train includes electrical pulses.
12. The method of claim 8 , wherein the received input pulse train includes optical pulses.
13. An apparatus for improving tolerance of input signal timing jitter, comprising:
means for recording the arrival times of at least two pulses within said input signal;
means for storing the arrival time of each pulse in a buffer;
means for determining from the stored arrival times a temporal relationship of the at least two pulses; and
means for assigning a binary value to a time slot determined by the temporal relationship of the pulses.
14. The apparatus of claim 13 , further comprising optical logic gates adapted to process an optical input signal.
15. The apparatus of claim 13 , further comprises electrical logic gates adapted to processes an electrical input signal.
16. The apparatus of claim 13 , wherein the means for determining and means for assigning further comprising:
means for extracting from the buffer a first arrival time associated with the first of the at least two pulses;
means for determining a first time slot number using the first arrival time;
means for assigning a logical “1” to the time slot associated with the first time slot number;
means for extracting from the buffer a second arrival time associated with the second of the at least two pulses;
means for determining a second time slot number using the second arrival time;
means for assigning a logical “1” to the time slot associated with a second time slot number; and
means for assigning a logical “0” to each time slot temporally positioned between the first and second time slots, the time slots having been assigned a logical “1”representing time slots associated with a valid input pulse.
17. The apparatus of claim 13 , wherein each time slot includes a time slot number N which is determined by N=t n /T, where t n is the arrival time of the n th pulse and 1/T is the digital transmission rate.
18. The apparatus of claim 13 , further comprising means for generating a local clock to provide at least two time stamps, each time stamp corresponds to the arrival time of the at least two pulses.
19. The apparatus of claim 18 , wherein the temporal relationship is the number of clock cycles separating the at least two pulses.