Adaptive cycle-slipped detector for unlock detection in phase-locked loop applications

1. An adaptive cycle-slipped detector (“ACSD”) for use in a Phase-Locked Loop (“PLL”) circuit, the ACSD comprising:

a phase comparator, the phase comparator configured to compare a reference signal from a frequency source and a feedback signal from the PLL circuit and to generate a phase feedback signal responsive to the comparison;

a phase shifter in signal communication with the phase comparator, the phase shifter configured to receive the reference signal and to generate a shifted reference signal; and

a cycle-slipped detector (“CSD”) in signal communication with the phase shifter, the CSD configured to compare the phases of the shifted reference signal and the feedback signal and generate a cycle-slipped signal responsive to the comparison.

2. The ACSD of claim 1 , wherein the cycle-slipped signal is asserted when the CSD detects more than one cycle of the feedback signal occurring within one cycle of the shifted reference signal or more than one cycle of the shifted reference signal occurring within one cycle of the feedback signal.

3. The ACSD of claim 2 , wherein the cycle-slipped signal is de-asserted when the CSD detects not more than one cycle of the feedback signal occurring within one cycle of the shifted reference signal and not more than one cycle of the shifted reference signal occurring within one cycle of the feedback cycle.

4. The ACSD of claim 3 , wherein the cycle-slipped signal is de-asserted responsive to a comparison of a predetermined value with a cycle-slip counter in signal communication with the CSD.

5. The ACSD of claim 4 , wherein the predetermined value is re-loadable into the cycle-slip counter.

6. The ACSD of claim 5 , wherein the ACSD is implemented as a monolithic integrated circuit (“IC”).

7. The ACSD of claim 1 , wherein the phase shifter shifts the phase of the reference signal responsive to the phase feedback signal from the phase comparator.

8. The ACSD of claim 7 , wherein the phase of the reference signal is shifted until an active edge of the reference signal coincides with a falling edge of the feedback signal.

9. The ACSD of claim 8 , wherein the phase shifter includes a delay-locked loop (“DDL”) circuit.

10. The ACSD of claim 8 , wherein the phase shifter includes means for manually adjusting the phase offset.

11. The ACSD of claim 1 , wherein the CSD includes a field-programmable gate array (“FPGA”).

12. A method for determining whether a feedback signal from a Phase-Locked Loop (“PLL”) circuit is locked to a reference signal from a frequency source, the method comprising:

comparing the phase of the feedback signal and the reference signal;

generating a phase feedback signal responsive to the comparison;

shifting the reference signal responsive to the phase feedback signal;

comparing the shifted reference signal and the feedback signal in a cycle-slip detector; and

generating a cycle-slipped signal responsive to the comparison.

13. The method of claim 12 , further including asserting the cycle-slipped signal when the cycle-slipped detector detects more than one cycle of the feedback signal occurring within one cycle of the shifted reference signal or more than one cycle of the shifted reference signal occurring within one cycle of the feedback signal.

14. The method of claim 13 , further including de-asserting the cycle-slipped signal when the cycle-slipped detector detects not more than one cycle of the feedback signal occurring within one cycle of the shifted reference signal and not more than one cycle of the shifted reference signal occurring within one cycle of the feedback signal.

15. The method of claim 14 , further including;

incrementing a cycle-slip counter for each cycle of the reference signal for which the cycle-slipped detector detects not more than one cycle of the feedback signal occurring within one cycle of the shifted reference signal and not more than one cycle of the shifted reference signal occurring within one cycle of the feedback signal;

comparing the cycle-slip counter to a predetermined value; and

de-asserting the cycle-slipped signal when the cycle-slip counter equals or exceeds the predetermined value.

16. The method of claim 15 , further including re-loading the predetermined value into the cycle-slip counter.

17. The method of claim 12 , further including shifting the phase of the reference signal until its active edge is aligned with the falling edge of the feedback signal.

18. The method of claim 17 , further including:

sampling the reference signal with the feedback signal until a one is sampled;

increasing the phase of the reference signal;

re-sampling the shifted reference signal;

repeating the steps of increasing the phase of the reference signal and re-sampling the shifted reference signal until a zero is sampled;

decreasing the phase of the reference signal;

re-sampling the shifted reference signal; and

repeating the steps of decreasing the phase of the reference signal and re-sampling the shifted reference signal until a one is sampled.

19. An adaptive cycle-slipped detector (“ACSD”) for use in a Phase-Locked Loop (“PLL”) circuit, the ACSD comprising:

a first means for comparing a reference signal from a frequency source and a feedback signal from the PLL circuit, and for generating a phase feedback signal responsive to the comparison;

a second means in signal communication with the first means, the second means for receiving the reference signal and for generating a shifted reference signal; and

a third means in signal communication with the second means, the third means for comparing the phases of the shifted reference signal and the feedback signal and for generating a cycle-slipped signal responsive to the comparison.

20. The ACSD of claim 19 ,

wherein the cycle-slipped signal is asserted when the third means detects more than one cycle of the feedback signal occurring within one cycle of the shifted reference signal or more than one cycle of the shifted reference signal occurring within one cycle of the feedback signal, and

wherein the cycle-slipped signal is de-asserted when the third means detects not more than one cycle of the feedback signal occurring within one cycle of the shifted reference signal and not more than one cycle of the shifted reference signal occurring within one cycle of the feedback cycle.