Semiconductor memory and memory controller therefor
View Patent ↗The present invention relates to AG-AND-type flash memory which reads management information about a plurality of clusters in a short time, wherein a plurality of clusters are arranged as rows of a matrix, and a plurality of banks are arranged as columns. Single management information is stored in specific pages of all blocks belonging to a certain cluster. For instance, management information (having contents C 0 ) about cluster is stored in specific pages of all blocks. Simultaneous access can be made to a plurality of the banks. Upon system startup, the management information is read obliquely such that the management information about cluster is read from bank 0; . . . , and such that the management information about cluster 3 is read from bank 3 . Accordingly, the management information about a plurality of the clusters can be read in a single access operation.
1. A semiconductor memory constructed by a plurality of memory cells, comprising:
pages which are units for executing reading and writing of data;
blocks, each of which is formed from a plurality of the pages;
a plurality of clusters, one or more of the plurality of clusters is formed from a plurality of the blocks; and
a plurality of banks to which simultaneous access can be made, wherein
one or more of the plurality of clusters are constructed by a plurality of blocks across a plurality of banks, and an identical set of unique information about at least one of the one or more cluster is stored in a specific position on specific pages of each block constructing the at least one of the one or more clusters, allowing for unique information about a plurality of the clusters to be read simultaneously by concurrently reading the single specific pages from a plurality of the banks when the unique information about a plurality of the clusters is read.
2. The semiconductor memory according to claim 1 , wherein the unique information is address information about all blocks constituting a certain cluster, and cluster management information including a conversion table of a physical address and a logical address.
3. A memory controller for reading unique information from semiconductor memory constructed by a plurality of memory cells, the semiconductor memory including: pages which are units for executing reading and writing of data; blocks, each of which is constructed by a plurality of the pages; a cluster which is constructed by a plurality of the blocks; and a plurality of banks to which simultaneous access can be made, a certain cluster being constructed by a plurality of blocks across a plurality of banks, and an identical set of unique information about the cluster being stored in a specific position on specific pages of each block constructing the cluster, wherein
all blocks forming a single cluster exist in separate banks; and
unique information about a plurality of the clusters is read simultaneously by concurrently reading the single specific pages from a plurality of the banks when the unique information about a plurality of the clusters is read in accordance with a read command from a higher-level system.
4. The memory controller according to claim 3 , wherein the semiconductor memory is arranged in a matrix pattern; a plurality of clusters “i” (“i” designates a positive integer) are arranged as rows of the matrix, and a plurality of banks “j” (“j” designates a positive integer) are arranged as columns of the same; and, when unique information is simultaneously read from a plurality of the banks, reading is performed in a diagonal direction where “i”=“j” is achieved.
5. The memory controller according to claim 3 , wherein the semiconductor memory is arranged in a matrix pattern; a plurality of clusters are arranged as rows of the matrix, and a plurality of banks are arranged as columns of the same; and, when unique information is simultaneously read from a plurality of the banks, reading is performed obliquely with respect to the matrix pattern.