IP Library Granted Patent US 7,487,344
Granted Patent B2
US 7,487,344 · App. 11/366,661 · Granted Feb 3, 2009

Implementing a microprocessor boot configuration prom within an FPGA

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Quick Facts
Patent No.
US 7,487,344
App. No.
11/366,661
Granted
Feb 3, 2009
Kind
B2
Abstract

A method and apparatus are provided for storing the boot configuration PROM of a microprocessor in an FPGA. The boot interface of the microprocessor, such as an I2C interface, leads to the FPGA instead of to a PROM. The boot configuration is stored as an image in the FPGA, and the microprocessor accesses the boot configuration using its normal boot interface. In this way, a dedicated boot PROM is not needed, saving real estate on the card on which the microprocessor is located. The boot configuration is also more easily modified, such as for version upgrades or diagnostics, than if the boot configuration were stored on a dedicated PROM. Different boot configurations may be stored as software images on a separate housekeeper processor, for loading into the FPGA.

Claims (24)

1. A circuit board comprising:

a field programmable device;

a first microprocessor having bootstrap pins through which the first microprocessor retrieves boot configuration data from the field programmable device; and

a second microprocessor, coupled to the field programmable device, that initiates a boot configuration of the first microprocessor,

wherein a definition of the boot configuration is altered by changing a software image stored within the second microprocessor.

2. The card of claim 1 wherein the field programmable device stores boot configuration data.

3. The card of claim 2 wherein the field programmable device is a Field Programmable Gate Array (FPGA).

4. The card of claim 3 wherein the FPGA stores boot configuration data as part of an I2C PROM emulation, and wherein the microprocessor accesses boot configuration data through an I2C interface.

5. The card of claim 4 , wherein the second processor is a housekeeper processor that stores a software image of the I2C PROM emulation for loading into the FPGA via an FPGA bitstream.

6. The card of claim 2 wherein the field programmable device is a Complex Programmable Logic Device.

7. A system for boot configuration of a microprocessor, comprising:

a slave card comprising:

a field programmable device, and

the microprocessor, the microprocessor having bootstrap pins through which the first microprocessor retrieves boot configuration data from the field programmable device; and

a housekeeper processor storing a software image for communicating boot configuration data to the field programmable device,

wherein the housekeeper processor initiates a boot configuration of the microprocessor and a definition of the boot configuration is altered by changing the software image stored within the housekeeper processor.

8. The system of claim 7 wherein the field programmable device is a Field Programmable Gate Array (FPGA), and wherein boot configuration data are communicated to the FPGA within an FPGA configuration bitstream.

9. The system of claim 8 wherein boot configuration data are communicated to the FPGA within an FPGA configuration bitstream for emulating an I2C PROM.

10. A method of boot configuration for a microprocessor, comprising:

downloading boot configuration data into a Field Programmable Gate Array (FPGA) via an FPGA bitstream from a housekeeping processor; and

downloading the boot configuration data from the FPGA through bootstrap pins into the microprocessor,

wherein the housekeeper processor initiates a boot configuration of the microprocessor and a definition of the boot configuration is altered by changing the software image stored within the housekeeper processor.

11. The method of claim 10 wherein the microprocessor and the FPGA are located on a first card, and wherein downloading the boot configuration comprises downloading the boot configuration via an FPGA bitstream originating from a housekeeper processor located on a second card.

12. The method of claim 11 wherein downloading the boot configuration comprises downloading the boot configuration via an FPGA bitstream for emulating an I2C PROM.

Assignments (12)
PATENT SECURITY AGREEMENT Recorded Aug 6, 2024
From: RPX CORPORATION; RPX CLEARINGHOUSE LLC
To: BARINGS FINANCE LLC, AS COLLATERAL AGENT
Reel/Frame 068328/0674 →
RELEASE OF LIEN ON PATENTS Recorded Aug 5, 2024
From: BARINGS FINANCE LLC
To: RPX CORPORATION
Reel/Frame 068328/0278 →
PATENT SECURITY AGREEMENT Recorded Apr 22, 2023
From: RPX CORPORATION
To: BARINGS FINANCE LLC, AS COLLATERAL AGENT
Reel/Frame 063429/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 28, 2021
From: PROVENANCE ASSET GROUP LLC
To: RPX CORPORATION
Reel/Frame 059352/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 30, 2021
From: NOKIA US HOLDINGS INC.
To: PROVENANCE ASSET GROUP HOLDINGS LLC; PROVENANCE ASSET GROUP LLC
Reel/Frame 058363/0723 →
RELEASE OF SECURITY INTEREST Recorded Nov 30, 2021
From: CORTLAND CAPITAL MARKETS SERVICES LLC
To: PROVENANCE ASSET GROUP HOLDINGS LLC; PROVENANCE ASSET GROUP LLC
Reel/Frame 058983/0104 →
ASSIGNMENT AND ASSUMPTION AGREEMENT Recorded Feb 14, 2019
From: NOKIA USA INC.
To: NOKIA US HOLDINGS INC.
Reel/Frame 048370/0682 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 13, 2017
From: NOKIA TECHNOLOGIES OY; NOKIA SOLUTIONS AND NETWORKS BV; ALCATEL LUCENT SAS
To: PROVENANCE ASSET GROUP LLC
Reel/Frame 043877/0001 →
SECURITY INTEREST Recorded Sep 13, 2017
From: PROVENANCE ASSET GROUP HOLDINGS, LLC; PROVENANCE ASSET GROUP LLC
To: NOKIA USA INC.
Reel/Frame 043879/0001 →
SECURITY INTEREST Recorded Sep 13, 2017
From: PROVENANCE ASSET GROUP HOLDINGS, LLC; PROVENANCE ASSET GROUP, LLC
To: CORTLAND CAPITAL MARKET SERVICES, LLC
Reel/Frame 043967/0001 →
CHANGE OF NAME Recorded Dec 17, 2008
From: ALCATEL
To: ALCATEL LUCENT
Reel/Frame 021990/0751 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 3, 2006
From: GRIEVE, RICHARD; MACDONALD, AARON MAXWELL; SCHRIEL, JAMES MICHAEL
To: ALCATEL
Reel/Frame 017659/0539 →