Method and apparatus for performing variable word width searches in a content addressable memory
View Patent ↗A content Addressable memory (CAM) for performing search operations using variable width search data, said CAM comprising a plurality of arrays of CAM cells, each coupled to a respective sub-search data bus, the sub-search buses being confined to form a main search data bus, to which is applied the search data; selector circuits receiving match line signals from respective CAM arrays, the match line signals being indicative of the results of a search and comparison formed in the associated CAM array, the selector circuit being responsive to a mode selection signal for selecting one or more of said match line output signals to be switched to a priority encoder and multiple match resolver (PE-MMR), wherein in a first mode the match line output signals are switched to said PE-MMR and in a second mode groups of match line output signals from selected arrays are switched to said PE-MMR.
1. A memory, comprising:
an array of content-addressable memory cells, wherein each row of the content-addressable memory cells is configured to store a wide word of data and at least one word of data; and
at least one search data bus coupled to each row of the content-addressable memory cells, wherein the at least one search data bus is configured to provide word search data to the at least one word of data and wide word search data to the wide word of data.
2. The memory of claim 1 , wherein the at least one word of data comprises at least one less bit than the wide word of data.
3. The memory of claim 1 , wherein the at least one word of data comprises a number of bits that is half a number of bits of the wide word of data.
4. The memory of claim 1 , further comprising another search data bus coupled to each row of another array of content-addressable memory cells, and wherein the another search data bus is configured to provide the word search data to the at least one word of data and the wide word search data to the wide word of data.
5. The memory of claim 4 , wherein the search data bus and the other search data bus are communicatively coupled and configured to communicate the word search data or the wide word search data in parallel to the two arrays.
6. The memory of claim 1 , further comprising a plurality of arrays that are searchable in parallel using the word search data or the wide word search data.
7. A method comprising:
storing a wide word of data and at least one word of data in at least one of a plurality of rows in an array of content-addressable memory cells; and
communicating word search data to the at least one word of data and wide word search data to the wide word of data via at least one search data bus that is communicatively coupled to the plurality of rows in the array of content- addressable memory cells.
8. The method of claim 7 , wherein the at least one word of data comprises at least one less bit than the wide word of data.
9. The method of claim 7 , wherein the at least one word of data comprises a number of bits that is half a number of bits of the wide word of data.
10. The method of claim 7 , further comprising:
storing the wide word of data and the at least one word of data in at least one of a plurality of rows in another array of content-addressable memory cells; and
communicating the word search data to the at least one word of data and the wide word search data to the wide word of data via another search data bus that is communicatively coupled to the plurality of rows in the other array of content-addressable memory cells.
11. The method of claim 10 , wherein said communicating the word search data or the wide word search data to the two arrays is performed in parallel.
12. The method of claim 7 , further comprising searching a plurality of arrays in parallel using the word search data or the wide word search data.
13. A system comprising:
means for storing a wide word of data and a word of data in at least one of a plurality of rows arranged in an array; and
means for communicating word search data to the word of data and wide word search data to the wide word of data, wherein the communicating means is communicatively coupled to the plurality of rows of the storing means.
14. The system of claim 13 , wherein the word of data comprises at least one less bit than the wide word of data.
15. The system of claim 13 , wherein the word of data comprises a number of bits that is half a number of bits of the wide word of data.
16. The system of claim 13 , further comprising:
a second means for storing the wide word of data and the word of data in at least one of a plurality of rows arranged in another array; and
a second means for communicating the word search data to the word of data and the wide word search data to the wide word of data, wherein the second communicating means is communicatively coupled to the plurality of rows of the second storing means.
17. The system of claim 16 , wherein the communicating means and the second communicating means are communicatively coupled to communicate the word search data or the wide word search data in parallel.
18. The system of claim 13 , further comprising a plurality of arrays that are searchable in parallel using the word search data or the wide word search data.