Electrical system including driver that provides a first drive strength and a second drive strength

1 . An electrical system, comprising:

a signal line that is terminated via a passive component; and

a driver configured to receive an input signal and provide an output signal via the signal line and to provide an output logic level in the output signal at a first drive strength and to switch and provide the output logic level in the output signal at a second drive strength, wherein the first drive strength is greater than the second drive strength.

2 . The electrical system of claim 1 , wherein the driver is configured to switch and provide the output logic level in the output signal at the second drive strength based on de-selection of a circuit that is configured to receive the output signal.

3 . The electrical system of claim 1 , wherein the driver is configured to switch and provide the output logic level in the output signal at the second drive strength based on the input signal remaining at an input logic level.

4 . The electrical system of claim 1 , wherein the driver is configured to switch and provide the output logic level in the output signal at the second drive strength based on a signal level of the output signal.

5 . The electrical system of claim 1 , wherein the driver is configured to switch and provide the output logic level in the output signal at the second drive strength based on time from a transition of the input signal.

6 . The electrical system of claim 1 , wherein the driver is configured to switch and provide the output logic level in the output signal at the second drive strength based on a combination of a signal level of the output signal and time from a transition of the input signal.

7 . The electrical system of claim 1 , wherein the first drive strength is at least ten times greater than the second drive strength.

8 . A memory system, comprising:

memory circuits including receivers configured to receive fly-by signals;

a bus that is terminated via at least one passive component and configured to communicate the fly-by signals to the receivers in the memory circuits; and

drivers configured to provide the fly-by signals to the receivers in the memory circuits via the bus, wherein each of the drivers is configured to provide a fly-by output signal at a first signal level to establish multiple receivers of the receivers at a logic level and to provide the fly-by output signal at a second signal level to maintain the multiple receivers at the logic level and save power in the memory system.

9 . The memory system of claim 8 , wherein the first signal level is at least 175 milli-volts from a reference value.

10 . The memory system of claim 8 , wherein the second signal level is less than 175 milli-volts from a reference value.

11 . The memory system of claim 8 , wherein the second signal level is less than 100 milli-volts from a reference value.

12 . The memory system of claim 8 , wherein the memory circuits are dynamic random access memory circuits that are part of a registered dual in-line memory module.

13 . The memory system of claim 8 , wherein the memory circuits are dynamic random access memory circuits that are part of a fully buffered dual in-line memory module.

14 . An electrical system, comprising:

means for receiving an input signal;

means for communicating an output signal that corresponds to the input signal;

means for providing an output logic level in the output signal at a first drive strength; and

means for switching to provide the output logic level in the output signal at a second drive strength that is less than the first drive strength.

15 . The electrical system of claim 14 , wherein the means for switching comprises means for switching to provide the output logic level in the output signal at the second drive strength based on de-selection of a circuit that is configured to receive the output signal.

16 . The electrical system of claim 14 , wherein the means for switching comprises means for switching to provide the output logic level in the output signal at the second drive strength based on the input signal remaining at an input logic level.

17 . The electrical system of claim 14 , wherein the means for switching comprises means for switching to provide the output logic level in the output signal at the second drive strength based on a signal level of the output signal.

18 . The electrical system of claim 14 , wherein the means for switching comprises means for switching to provide the output logic level in the output signal at the second drive strength based on time from a transition of the input signal.

19 . The electrical system of claim 14 , wherein the means for switching comprises means for switching to provide the output logic level in the output signal at the second drive strength based on a combination of a signal level of the output signal and time from a transition of the input signal.

20 . A method of driving an output signal on a terminated signal line, comprising:

receiving an input signal;

communicating the output signal that corresponds to the input signal;

providing an output logic level in the output signal at a first drive strength; and

switching to provide the output logic level in the output signal at a second drive strength that is less than the first drive strength.

21 . The method of claim 20 , wherein switching comprises:

switching to provide the output logic level in the output signal at the second drive strength based on de-selection of a circuit that is configured to receive the output signal.

22 . The method of claim 20 , wherein switching comprises:

switching to provide the output logic level in the output signal at the second drive strength based on the input signal remaining at an input logic level.

23 . The method of claim 20 , wherein switching comprises:

switching to provide the output logic level in the output signal at the second drive strength based on a signal level of the output signal.

24 . The method of claim 20 , wherein switching comprises:

switching to provide the output logic level in the output signal at the second drive strength based on time from a transition of the input signal.

25 . A method of driving fly-by signals on a terminated bus to receivers in memory circuits, comprising:

receiving fly-by signals at the receivers;

communicating the fly-by signals to the receivers via the terminated bus; and

providing a fly-by output signal at a first signal level to establish multiple receivers of the receivers at a logic level; and

providing the fly-by output signal at a second signal level that maintains the multiple receivers at the logic level and saves power.

26 . The method of claim 25 , wherein providing a fly-by output signal at a first signal level comprises:

providing the fly-by output signal at the first signal level of at least 175 milli-volts from a reference value.

27 . The method of claim 25 , wherein providing the fly-by output signal at a second signal level comprises:

providing the fly-by output signal at the second signal level of less than 175 milli-volts from a reference value.

28 . The method of claim 25 , wherein providing the fly-by output signal at a second signal level comprises:

providing the fly-by output signal at the second signal level of less than 100 milli-volts from a reference value.