IP Library Granted Patent US 7,402,507
Granted Patent B2
US 7,402,507 · App. 11/367,725 · Granted Jul 22, 2008

Semiconductor package fabrication

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Quick Facts
Patent No.
US 7,402,507
App. No.
11/367,725
Granted
Jul 22, 2008
Kind
B2
Abstract

A semiconductor package fabrication method in which drop on demand deposition of a drop on demand depositable material is used to prepare one component or a plurality of components of a semiconductor package or multi-chip module.

Claims (30)

1. A method of preparing a semiconductor package comprising:

identifying a reference mark on a semiconductor package component;

positioning a drop on demand head capable of depositing drop depositable material based on said identified reference mark; and

depositing said depositable material on a surface of said semiconductor package component to realize a pattern.

2. The method of claim 1 , wherein said semiconductor package component is a semiconductor die.

3. The method of claim 2 , wherein said semiconductor die is a part of a semiconductor wafer.

4. The method of claim 1 , wherein said semiconductor package component is a MOSFET, an IGBT, a diode, a HEMT, a bipolar transistor, a JFET, or an integrated circuit.

5. The method of claim 1 , wherein said depositable material is a dielectric.

6. The method of claim 1 , wherein said depositable material is an electrically conductive material.

7. The method of claim 1 , wherein said semiconductor package component is a portion of a lead frame.

8. The method of claim 1 , wherein said semiconductor package component is a conductive can.

9. The method of claim 1 , wherein said depositable material is a polymer alloy.

10. The method of claim 9 , wherein said polymer alloy includes a silicon epoxy.

11. The method of claim 9 , wherein said polymer alloy includes a silicon polyester.

12. The method of claim 9 , wherein said polymer alloy includes an acrylate.

13. The method of claim 1 , wherein said depositable material includes an organopolysiloxane.

14. The method of claim 1 , wherein said semiconductor package component is part of a multi-chip module.

15. A method for fabricating a semiconductor device comprising:

forming a conductive body, said conductive body including a material susceptible to consumption by a solder;

depositing a barrier atop said conductive body, said barrier being capable of preventing the consumption of said material that is susceptible of consumption; and

depositing a solderable body atop said barrier; wherein said barrier is deposited through a drop on demand process, or said barrier is screen printed.

16. The method of claim 15 , wherein said material susceptible of consumption comprises silver.

17. The method of claim 15 , wherein said barrier comprises nickel.

18. The method of claim 15 , wherein said solderable body includes silver.

19. The method of claim 15 , wherein said barrier is comprised of nickel, and said solderable body is comprised of silver.

20. The method of claim 15 , wherein said material susceptible of consumption is silver, said barrier is comprised of nickel, and said solderable body includes silver.

21. A method of fabricating an MCM comprising:

drop on demand depositing conductive tracks and dielectric bodies on a leadframe to form an integrated circuit body capable of receiving semiconductor devices; and

drop on demand depositing of identifying indicia on said leadframe.

22. The method of claim 21 , wherein said indicia includes part number or date of fabrication.

Assignments (2)
CHANGE OF NAME Recorded Jul 23, 2018
From: INTERNATIONAL RECTIFIER CORPORATION
To: INFINEON TECHNOLOGIES AMERICAS CORP.
Reel/Frame 046612/0968 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 22, 2006
From: STANDING, MARTIN; PAVIER, MARK; CLARKE, ROBERT J.; SAWLE, ANDREW; MCCARTNEY, KENNETH
To: INTERNATIONAL RECTIFIER CORPORATION
Reel/Frame 017911/0011 →