Method, circuit and system for detecting a locked state of a clock synchronization circuit
Locked state detection circuits, devices, systems, and methods for detecting a locked or synchronized state of a clock synchronization circuit are described. Detection of a locked state includes a circuit including a phase detector configured to generate a delay adjustment signal in response to comparison of a forward path signal indicative of an external clock signal and a feedback path signal indicative of an output clock signal. The circuit further includes a trend detector operably coupled to the delay adjustment signal and configured to generate a locked signal indicative of an in-phase steady-state between the external clock signal and the output clock signal.
1 . A clock synchronization circuit, comprising:
a delay line having first and second inputs and an output, the first input configured to receive an external clock signal via an input driver and the output configured to couple with an output driver to generate an output clock signal;
an I/O model having an output and an input, the input of the I/O model configured to couple with the output of the delay line, the I/O model further configured to model delay of the output driver and the input driver;
a phase detector including forward and feedback path inputs and an output operably coupled to the second input of the delay line, the forward path input coupled to the first input of the delay line and the feedback path input coupled to the output of the I/O model, the phase detector configured to generate a delay adjustment signal; and
a trend detector having an input operably coupled to the second input of the delay line and configured to generate a locked signal on an output, the locked signal indicative of an in-phase steady-state between the external clock signal and the output clock signal.
2 . The circuit of claim 1 , further comprising a filter operably coupled between the phase detector and the delay line and the trend detector, the filter configured to suppress noise variations from the output of the phase detector prior to being received at the delay line and the trend detector.
3 . The circuit of claim 1 , wherein the trend detector comprises an oscillation detector having an input operably coupled to the second input of the delay line and configured to generate the locked signal, the locked signal indicative of the in-phase steady-state between the external clock signal and the output clock signal.
4 . The circuit of claim 3 , wherein the oscillation detector is configured to be configurable to a range of the in-phase steady-state of the external clock signal and the output clock signal.
5 . The circuit of claim 4 , wherein the trend detector further comprises a delay counter operably coupled to the oscillation detector, the delay counter configured to generate the locked signal following a stability duration when the delay adjustment signal remains within the range.
6 . The circuit of claim 1 , wherein the trend detector comprises a sequential directional delay shift detector having an input operably coupled to the second input of the delay line and configured to generate the locked signal, the locked signal indicative of the in-phase steady-state between the external clock signal and the output clock signal.
7 . The circuit of claim 6 , wherein the sequential directional delay shift detector is configured to be configurable to a range specifying the in-phase steady-state between the external clock signal and the output clock signal.
8 . The circuit of claim 7 , wherein the trend detector further comprises a delay counter operably coupled to the sequential directional delay shift detector, the delay counter configured to generate the locked signal following a stability duration when the delay adjustment signal remains within the range.
9 . A delay locked loop circuit, comprising:
a phase detector configured to generate a delay adjustment signal in response to comparison of a forward path signal indicative of an external clock signal and a feedback path signal indicative of an output clock signal; and
a trend detector operably coupled to the delay adjustment signal and configured to generate a locked signal indicative of an in-phase steady-state between the external clock signal and the output clock signal.
10 . The delay locked loop circuit of claim 9 , wherein the trend detector is configured to monitor oscillations of the delay adjustment signal and generate the locked signal when the oscillations remain within a range.
11 . The delay locked loop circuit of claim 10 , wherein the trend detector is further configured to delay generation of the locked signal until the oscillations remain within the range for a stability duration.
12 . The delay locked loop circuit of claim 9 , wherein the trend detector is configured to detect sequential directional delay shifts of the delay adjustment signal and generate the locked signal when the shifts remain within a range.
13 . The delay locked loop circuit of claim 12 , wherein the trend detector is further configured to delay generation of the locked signal until the shifts remain within the range for a stability duration.
14 . A memory device, comprising:
a memory array with an output driver coupled thereto; and
a delay locked loop circuit operably coupled between the output driver and configured to couple with an external clock signal, the delay locked loop circuit including:
a phase detector configured to generate a delay adjustment signal in response to comparison of a forward path signal indicative of an external clock signal and a feedback path signal indicative of an output clock signal; and
a trend detector operably coupled to the delay adjustment signal and configured to generate a locked signal indicative of an in-phase steady-state between the external clock signal and the output clock signal.
15 . The memory device of claim 14 , wherein the trend detector is configured to monitor oscillations of the delay adjustment signal and generate the locked signal when the oscillations remain within a range.
16 . The memory device of claim 15 , wherein the trend detector is further configured to delay generation of the locked signal until the oscillations remain within the range for a stability duration.
17 . The memory device of claim 14 , wherein the trend detector is configured to detect sequential directional delay shifts of the delay adjustment signal and generate the locked signal when the shifts remain within a range.
18 . The memory device of claim 17 , wherein the trend detector is further configured to delay generation of the locked signal until the shifts remain within the range for a stability duration.
19 . A semiconductor wafer comprising a plurality of integrated circuit memory devices, each memory device comprising:
a memory array with an output driver coupled thereto; and
a delay locked loop circuit operably coupled between the output driver and configured to couple with an external clock signal, the delay locked loop circuit including:
a phase detector configured to generate a delay adjustment signal in response to comparison of a forward path signal indicative of an external clock signal and a feedback path signal indicative of an output clock signal; and
a trend detector operably coupled to the delay adjustment signal and configured to generate a locked signal indicative of an in-phase steady-state between the external clock signal and the output clock signal.
20 . An electronic device, comprising:
a processor;
at least one of an input device and an output device operably coupled to the processor; and
a memory device operably coupled to the processor, the memory device including a memory array with an output driver coupled thereto and a delay locked loop circuit operably coupled between the output driver and configured to couple with an external clock signal, the delay locked loop circuit including:
a phase detector configured to generate a delay adjustment signal in response to comparison of a forward path signal indicative of an external clock signal and a feedback path signal indicative of an output clock signal; and
a trend detector operably coupled to the delay adjustment signal and configured to generate a locked signal indicative of an in-phase steady-state between the external clock signal and the output clock signal.
21 . The electronic system of claim 20 , wherein the trend detector is configured to monitor oscillations of the delay adjustment signal and generate the locked signal when the oscillations remain within a range.
22 . The electronic system of claim 21 , wherein the trend detector is further configured to delay generation of the locked signal until the oscillations remain within the range for a stability duration.
23 . The electronic system of claim 20 , wherein the trend detector is configured to detect sequential directional delay shifts of the delay adjustment signal and generate the locked signal when the shifts remain within a range.
24 . The electronic system of claim 23 , wherein the trend detector is further configured to delay generation of the locked signal until the shifts remain within the range for a stability duration.
25 . A signal locking indication method, comprising:
generating a delay adjustment signal in response to comparison of a forward path signal indicative of an external clock signal and a feedback path signal indicative of an output clock signal; and
detecting a trend of the delay adjustment signal; and
generating a locked signal indicative of an in-phase steady-state between the external clock signal and the output clock signal.
26 . The method of claim 25 , wherein the detecting a trend comprises detecting oscillations of the delay adjustment signal and generating the locked signal when the oscillations remain within a range.
27 . The method of claim 26 , further comprising delaying generation of the locked signal until the oscillations remain within the range for a stability duration.
28 . The method of claim 25 , wherein the detecting a trend comprises detecting sequential directional delay shifts of the delay adjustment signal and generating the locked signal when the shifts remain within a range.
29 . The method of claim 28 , further comprising delaying generation of the locked signal until the shifts remain within the range for a stability duration.