Variable power adaptive transmitter

1. A circuit comprising:

a delay module that receives a digital transmit signal and that generates a delayed transmit signal;

a first digital to analog converter that converts said delayed transmit signal to an analog transmit signal;

an analog output circuit that receives said analog transmit signal;

an envelope generating module that generates a digital envelope signal based on amplitude information related to said digital transmit signal;

a supply adjustment module that supplies a voltage supply reference when said digital envelope signal is less than said voltage supply reference and that boosts a bias voltage of said analog output circuit to a voltage level that is greater than a voltage level of said digital envelope signal when said digital envelope signal is greater than said voltage supply reference;

a second digital to analog converter that converts said digital envelope signal to an analog envelope signal, wherein said first digital to analog converter has a higher resolution than said second digital to analog converter; and

a third digital to analog converter that receives said digital envelope signal and generates an analog output signal and that selectively boosts a bias current for said analog output circuit based on said analog output signal.

2. The circuit of claim 1 , wherein said bias current increases when said digital envelope signal exceeds said voltage supply reference.

3. A wired network interface comprising the circuit of claim 1 .

4. A wireless network interface comprising the circuit of claim 1 .

5. The wireless network interface of claim 4 , wherein said wireless network interface is compliant with at least one of IEEE section 802.11, 802.11a, 802.11b, 802.11g, 802.11h, 802.11n, 802.16, and 802.20.

6. The circuit of claim 1 , wherein said envelope generating module receives said digital transmit signal and generates said digital envelope signal based on said digital transmit signal.

7. The circuit of claim 1 , wherein a rise time of said digital envelope signal is slower than a fastest rise time of said analog transmit signal.

8. The circuit of claim 1 wherein said envelope generating module generates said envelop signal based on voltage amplitude of the digital transmit signal.

9. The circuit of claim 1 , wherein said supply adjustment module comprises:

a switch that is connected to said analog output circuit and that receives said voltage supply reference; and

a capacitance that is connected between said first digital to analog converter and said switch.

10. The circuit of claim 9 , wherein said switch is in a first state when said supply adjustment module biases said analog output circuit with said voltage supply reference, and

wherein said switch is in a second state when said supply adjustment module biases said analog output circuit with said voltage level that is greater than said voltage level of said envelope signal.

11. The circuit of claim 9 , wherein said switch is directly connected to said capacitance.

12. The circuit of claim 9 , wherein said switch and said capacitance are directly connected to said analog output circuit.

13. The circuit of claim 9 , wherein said capacitance is directly connected to said first digital to analog converter.

14. A circuit comprising:

a delay module that receives a digital transmit signal and that generates a delayed transmit signal;

a first digital to analog converter that converts said delayed transmit signal to an analog transmit signal;

an analog output circuit that receives said analog transmit signal;

a supply boost module that samples a signal including amplitude information of said digital transmit signal and that selectively boosts a voltage supply reference supplied to said analog output circuit before a corresponding portion of said analog transmit signal is received by said analog output circuit based on a difference between said sampled signal and said voltage supply reference,

wherein said supply boost module includes:

an envelope generating module that generates a digital envelope signal;

a second digital to analog converter that converts said digital envelope signal to an analog envelope signal; and

a supply adjustment module that supplies said voltage supply reference when said digital envelope signal is less than said voltage supply reference and that boosts a bias voltage of said analog output circuit to a voltage level that is greater than said voltage supply reference when said digital envelope signal exceeds said voltage supply reference; and

a third digital to analog converter that receives said digital envelope signal and that generates a bias current for said analog output circuit.

15. The circuit of claim 14 , wherein said first digital to analog converter has a higher resolution than said second digital to analog converter.

16. The circuit of claim 14 , wherein said bias current increases when said digital envelope signal exceeds said voltage supply reference.

17. A wired network interface comprising the circuit of claim 14 .

18. A wireless network interface comprising the circuit of claim 14 .

19. The wireless network interface of claim 18 , wherein said wireless network interface is compliant with at least one of IEEE section 802.11, 802.11a, 802.11b, 802.11g, 802.11h, 802.11n, 802.16, and 802.20.

20. The circuit of claim 14 , wherein said envelope generating module receives said digital transmit signal and generates said envelope signal based on said digital transmit signal.

21. The circuit of claim 14 , wherein said digital envelope signal has a rise time that is slower than a fastest rise time of said analog transmit signal.

22. The circuit of claim 14 , wherein said analog output circuit receives a differential bias and wherein said supply boost module one of symmetrically and asymmetrically biases said analog output circuit.

23. A method comprising:

receiving a digital transmit signal;

generating a delayed transmit signal;

converting said delayed transmit signal to an analog transmit signal;

receiving said analog transmit signal at an analog output circuit;

generating a digital envelope signal based on amplitude information related to said digital transmit signal;

supplying a voltage supply reference when said digital envelope signal is less than said voltage supply reference;

boosting a bias voltage of said analog output circuit to a voltage level that is greater than a voltage level of said digital envelope signal when said digital envelope signal is greater than said voltage supply reference;

converting said digital envelope signal to a first analog envelope signal;

converting said first analog envelope signal to a second analog envelope signal with said bias voltage; and

selectively boosting a bias current for said analog output circuit based on said second analog envelope signal.

24. The method of claim 23 , wherein said bias current increases when said digital envelope signal exceeds said voltage supply reference.

25. The method of claim 23 , wherein said digital envelope signal is based on said digital transmit signal.

26. The method of claim 23 , wherein said digital envelope signal has a rise time that is slower than a fastest rise time of said analog transmit signal.

27. The method of claim 23 , further comprising one of symmetrically and asymmetrically biasing said analog output circuit.

28. A method comprising:

receiving a digital transmit signal;

generating a delayed transmit signal;

converting said delayed transmit signal to an analog transmit signal;

receiving said analog transmit signal at an analog output circuit;

sampling a signal that includes amplitude information of said transmit signal and selectively boosting a voltage supply reference supplied to said analog output circuit before a corresponding portion of said analog transmit signal is received by said analog output circuit based on a difference between said sampled signal and said voltage supply reference;

generating a digital envelope signal;

converting said digital envelope signal to an analog envelope signal;

supplying said voltage supply reference when said digital envelope signal is less than a threshold and boosting a bias voltage of said analog output circuit to a voltage level that is greater than said voltage supply reference when said digital envelope signal exceeds said threshold;

converting said digital envelope signal to an analog output signal; and

generating a bias current for said analog output circuit.

29. The method of claim 28 , further comprising increasing said bias current when said digital envelope signal exceeds said threshold.

30. The method of claim 28 , wherein said digital envelope signal is based on said digital transmit signal.

31. The method of claim 28 , wherein said voltage supply reference has a rise time that is slower than a fastest rise time of said analog transmit signal.

32. The method of claim 28 , further comprising one of symmetrically and asymmetrically biasing said analog output circuit.

33. A circuit comprising:

a delay module that receives a digital transmit signal and that generates a delayed transmit signal;

a first digital to analog converter that converts said delayed transmit signal to an analog transmit signal;

an analog output circuit that receives said analog transmit signal;

an envelope generating module that generates an envelope signal based on amplitude information related to said digital transmit signal; and

a supply adjustment module that supplies a voltage supply reference when said envelope signal is less than said voltage supply reference and that boosts a bias voltage of said analog output circuit to a voltage level that is greater than a voltage level of said envelope signal when said envelope signal is greater than said voltage supply reference,

wherein said analog output circuit receives a differential bias and wherein said supply adjustment module one of symmetrically and asymmetrically biases said analog output circuit.

34. A circuit comprising:

a delay module that receives a digital transmit signal and that generates a delayed transmit signal;

a first digital to analog converter that converts said delayed transmit signal to an analog transmit signal;

an analog output circuit that receives said analog transmit signal;

an envelope generating module that generates an envelope signal based on amplitude information related to said digital transmit signal; and

a supply adjustment module that supplies a voltage supply reference when said envelope signal is less than said voltage supply reference and that boosts a bias voltage of said analog output circuit to a voltage level that is greater than a voltage level of said envelope signal when said envelope signal is greater than said voltage supply reference,

wherein said supply adjustment module comprises:

a first switch that is connected to said analog output circuit and that receives said voltage supply reference at a first polarity;

a second switch that is connected to said analog output circuit and that receives said voltage supply reference at a second polarity;

a first capacitance that is connected between said first digital to analog converter and said first switch; and

a second capacitance that is connected between a second digital to analog converter and said second switch.