Test vector manager, method of managing test vectors and a test tool employing the manager and the method
View Patent ↗The present invention provides a test vector manager for use with a unit under test (UUT). In one embodiment, the test vector manager includes a gateway device, coupled to the UUT, configured to provide a testing pathway for the UUT to coordinate test requests and responses for a backplane multi-drop test bus. The test vector manager also includes a test memory, coupled to the gateway device, configured to retrieve version-specific test vectors, which are resident on the UUT and correspond to the test requests. The test vector manager further includes a chain configuration logic unit, coupled to the test memory, configured to return the version-specific test vectors to the backplane multi-drop test bus employing the testing pathway. Alternatively, the test vector manager is further configured to connect the backplane multi-drop test bus to local UUT test bus and scan chain interfaces for tests using the version-specific test vectors.
1. A test vector manager for use with a unit under test (UUT), comprising:
a gateway device coupled to the UUT and configured to provide a testing pathway for the UUT to coordinate test requests and responses for a backplane multi-drop test bus;
a test memory coupled to the gateway device and configured to retrieve version-specific test vectors, which are resident on the UUT and correspond to the test requests; and
a chain configuration logic unit coupled to the test memory and configured to return the version-specific test vectors to the backplane multi-drop test bus employing the testing pathway.
2. The manager as recited in claim 1 wherein the chain configuration logic unit is further configured to connect the backplane multi-drop test bus to local UUT test bus and scan chain interfaces for tests using the version-specific test vectors.
3. The manager as recited in claim 1 wherein the version-specific test vectors are obtained from the UUT without application logic of the UUT being operational or functional.
4. The manager as recited in claim 1 wherein the version-specific test vectors are obtained from the UUT without impacting normal operation of the UUT.
5. The manager as recited in claim 1 wherein retrieval of the version-specific test vectors is independent of either UUT version or type.
6. The manager as recited in claim 1 wherein retrieval of the version-specific test vectors is accomplished as part of a boundary scan test infrastructure.
7. The manager as recited in claim 1 wherein the test memory is configured to be compliant with the IEEE 1149.1 standard and employ a memory element selected from the group consisting of:
a programmable read-only memory (PROM); and
a flash memory.
8. The manager as recited in claim 1 wherein the test memory is configured to provide a configuration pulse signal to the chain configuration logic thereby changing a local boundary scan chain configuration.
9. The manager as recited in claim 1 wherein the chain configuration logic unit is configured to employ a complex programmable logic device (cPLD).
10. A method of managing test vectors for a unit under test (UUT); comprising:
providing a testing pathway for the UUT to coordinate test requests and responses through a backplane multi-drop test bus;
retrieving version-specific test vectors, which are resident on the UUT and correspond to the test requests; and
returning the version-specific test vectors to the backplane multi-drop test bus employing the testing pathway.
11. The method as recited in claim 10 further comprising connecting the backplane multi-drop test bus to local UUT test bus and scan chain interfaces for tests using the version-specific test vectors.
12. The method as recited in claim 10 wherein the version-specific test vectors are obtained from the UUT without application logic of the UUT being operational or functional.
13. The method as recited in claim 10 wherein the version-specific test vectors are obtained from the UUT without impacting normal operation of the UUT.
14. The method as recited in claim 10 wherein retrieval of the version-specific test vectors is independent of either UUT version or type.
15. The method as recited in claim 10 wherein retrieval of the version-specific test vectors is accomplished as part of a boundary scan test infrastructure.
16. The method as recited in claim 10 wherein retrieving the version-specific test vectors is compliant with the IEEE 1149.1 standard and employs a memory element selected from the group consisting of:
a programmable read-only memory (PROM); and
a flash memory.
17. The method as recited in claim 10 wherein retrieving the version-specific test vectors employs a configuration pulse signal to change a local boundary scan chain configuration.
18. The method as recited in claim 10 wherein returning the version-specific test vectors employs a complex programmable logic device (cPLD).
19. A test tool, comprising:
a system test controller;
a backplane multi-drop test bus coupled to the system test controller;
a unit under test (UUT) coupled to the backplane multi-drop test bus;
a test vector manager, coupled to the UUT, including:
a gateway device that provides a testing pathway for the UUT to coordinate test requests and responses with the system test controller through the backplane multi-drop test bus,
a test memory, coupled to the gateway device, that retrieves version-specific test vectors, which are resident on the UUT and correspond to the test requests, and
a chain configuration logic unit, coupled to the test memory, that returns the version-specific test vectors to the backplane multi-drop test bus employing the testing pathway; and
a UUT local test structure, coupled to the test vector manager, that provides local UUT test bus and scan chain interfaces for tests using the version-specific test vectors.
20. The test tool as recited in claim 19 wherein the version-specific test vectors are obtained from the UUT without application logic of the UUT being operational or functional.
21. The test tool as recited in claim 19 wherein the version-specific test vectors are obtained from the UUT without impacting normal operation of the UUT.
22. The test tool as recited in claim 19 wherein retrieval of the version-specific test vectors is independent of either UUT version or type.
23. The test tool as recited in claim 19 wherein retrieval of the version-specific test vectors is accomplished as part of a boundary scan test infrastructure.
24. The test tool as recited in claim 19 wherein the test memory is compliant with the IEEE 1149.1 standard and employs a memory element selected from the group consisting of:
a programmable read-only memory (PROM); and
a flash memory.
25. The test tool as recited in claim 19 wherein the test memory provides a configuration pulse signal to the chain configuration logic thereby changing a local boundary scan chain configuration.
26. The test tool as recited in claim 19 wherein the chain configuration logic unit is configured to employ a complex programmable logic device (cPLD).