Gate driver using a multiple power supplies voltages and having a shift resister
View Patent ↗In a gate driver including a plurality of stages sequentially outputting shifted signals, each of the stages includes a first controller for controlling a first node in response to a first scan signal and a second scan signal; a second controller for controlling second and third nodes in response to the first scan signal and a voltage at the first node; and an output unit for selectively outputting one of a plurality of clock signals and a first power supply voltage in response to voltages at the first, second and third nodes, wherein second and third power supply voltages different from each other are switched to be supplied to the second and third nodes.
1. A gate driver using a multiple power supplies voltages and having a shift resister comprising a plurality of stages sequentially outputting shifted signals, each of the stages including:
a first controller for controlling a first node voltage in response to an output signal from a previous stage and an output signal from a next stage;
a second controller for controlling second and third nodes voltages in response to the output signal from the previous stage and the voltage at the first node; and
an output unit for selectively outputting one of a plurality of clock signals and a first power supply voltage in response to the voltages at the first, second and third nodes,
wherein second and third power supply voltages different from each other change their polarities at n frame periods(where n is a positive integer) and are supplied to the second and third nodes,
wherein each of the second and third power supply voltages oscillates between a high voltage and a low voltage, and the second and third power supply voltages different from each other are switched be supplied to the second and third nodes,
wherein the low voltage is lower than or equal to the voltage of the first power supply,
wherein the high voltage is higher than the voltage of the first power supply,
wherein the first controller comprises a first transistor for supplying a fourth power supply voltage to the first node in response to the output signal from the previous stage, a second transistor for supplying the first power supply voltage to the first node in response to the voltage at the second node, a third transistor for supplying the first power supply voltage to the first node in response to the voltage at the third node and a fourth transistor for supplying the first power supply voltage to the first node in response to the output signal of the next stage.
2. The gate driver using a multiple power supplies voltages and having a shift resister according to claim 1 , wherein the first controller further comprises a fifth transistor connected to the first transistor to supply the fourth power supply voltage to the first node in response to a second clock leading the one of the plurality of clock signals.
3. The gate driver using a multiple power supplies voltages and having a shift resister according to claim 1 , wherein the first controller further comprises a fifth transistor connected to the fourth transistor to supply the first power supply voltage to the first node in response to a second clock signal following the one of the plurality of clock signals.
4. The gate driver using a multiple power supplies voltages and having a shift resister according to claim 1 , wherein the second controller comprises:
a first transistor for supplying the second power supply voltage to the second node;
a second transistor for supplying the third power supply voltage to the third node;
a third transistor for supplying the first power supply voltage to the second node in response to the output signal of the previous stage;
a fourth transistor for supplying the first power supply voltage to the third node in response to the output signal of the previous stage;
a fifth transistor for supplying the first power supply voltage to the second node in response to the voltage at the first node; and
a sixth transistor for supplying the first power supply voltage to the third node in response to the voltage at the first node.
5. The gate driver using a multiple power supp lies voltages and having a shift resister according to claim 4 , wherein the second controller further comprises:
a seventh transistor supplying the first power supply voltage to the first node for controlling the first transistor; and
an eighth transistor supplying the first power supply voltage in response to the voltage at the first node for controlling the second transistor.
6. The gate driver using a multiple power supplies voltages and having a shift resister according to claim 5 , wherein the first transistor is controlled by a difference between the second power supply voltage and the first power supply voltage passing through the seventh transistor.
7. The gate driver using a multiple power supplies voltages and having a shift resister according to claim 5 , wherein the second transistor is controlled by a difference between the third power supply voltage inputted from the second transistor and the first power supply voltage passing through the eighth transistor.
8. The gate driver using a multiple power supplies voltages and having a shift resister according to claim 4 , wherein the second controller further comprises:
a seventh transistor supplying the first power supply voltage to the third node in response to the voltage at the second node;
an eighth transistor supplying the first transistor voltage to the second node in response to the voltage at the third node;
a ninth transistor supplying the second power supply voltage to the second node in response to the output signal of the next stage; and
a tenth transistor supplying the third power supply voltage to the third node in response to the output signal of the next stage.
9. The gate driver using a multiple power supplies voltages and having a shift resister according to claim 4 , wherein the second controller further comprises:
a seventh transistor supplying the first power supply voltage to the third node in response to the voltage from the second power supply;
an eighth transistor supplying the first power supply voltage to the second node in response to the voltage from the third power supply;
a ninth transistor supplying the second power supply voltage to the second node in response to the output signal of the next stage; and
a tenth transistor supplying the third power supply voltage to the third node in response to the output signal of the next stage.
10. The gate driver using a multiple power supplies voltages and having a shift resister according to claim 8 , wherein one of the second and third nodes is rapidly discharged by a control of the seventh to tenth transistors.
11. The gate driver using a multiple power supplies voltages and having a shift resister according to claim 1 , wherein the output unit comprises:
a first transistor for outputting the one of the plurality of the clock signals in response to the voltage at the first node;
a second transistor for outputting the first power supply voltage in response to the voltage at the second node; and
a third transistor for outputting the first power supply voltage in response to the voltage at the third node.
12. The gate driver using a multiple power supplies voltages and having a shift resister according to claim 1 , wherein the second and third power supply voltages are switched at n frame periods (where n is a positive integer).
13. The gate driver using a multiple power supplies voltages and having a shift resister according to claim 3 , wherein only one clock among clock signals of at least two phases is inputted to the respective stages.