Ultra low power ASIP architecture
View Patent ↗A microcomputer architecture comprises a microprocessor unit and a first memory unit, the microprocessor unit comprising a functional unit and at least one data register, the functional unit and the at least one data register being linked to a data bus internal to the microprocessor unit. The data register is a wide register comprising a plurality of second memory units which are capable to each contain one word. The wide register is adapted so that the second memory units are simultaneously accessible by the first memory unit, and so that at least part of the second memory units are separately accessible by the functional unit.
1. A microcomputer architecture comprising:
a microprocessor unit comprising a functional unit having a width of one word and a data register, the functional unit and the data register being linked to a data bus internal to the microprocessor unit; and
a first memory unit, wherein the data register is a wide register comprising a plurality of second memory units which are capable to each contain one word, the wide register being adapted so that the second memory units are simultaneously accessible by the first memory unit, and at least part of the second memory units are separately accessible by the functional unit, wherein the data register has a width determined by the number of second memory units in the data register,
wherein the data register is a single-ported register.
2. The microcomputer architecture according to claim 1 , wherein the microprocessor unit and the first memory unit being coupled to a system bus having a bus width, the plurality of second memory units in the wide register together having a register width, wherein the bus width equals the register width.
3. The microcomputer architecture according to claim 2 , the first memory unit having a line width, wherein the bus width equals the line width of the first memory unit.
4. The microcomputer architecture according to claim 2 , the first memory unit having a line width, wherein the bus width equals the line width.
5. The microcomputer architecture according to claim 1 , wherein the microprocessor unit further comprises a selector for selecting words in the data register.
6. The microcomputer architecture according to claim 5 , wherein the selector is a multiplexer configured to select words to be read from the data register.
7. The microcomputer architecture according to claim 6 , wherein the functional unit is an application specific unit coupled to the multiplexer for processing selected data from the data register.
8. The microcomputer architecture according to claim 6 , wherein the functional unit is a general purpose unit coupled to the multiplexer for processing selected data from the data register.
9. The microcomputer architecture according to claim 5 , wherein the selector comprises a demultiplexer configured to select, in the data register, words to be written.
10. The microcomputer architecture according to claim 5 , the microcomputer architecture further comprises at least a memory management unit for transferring data from and to the first memory unit to and from the data register, wherein each of the functional unit, the memory management unit and the selector has their own instruction buffer associated therewith.
11. The microcomputer architecture according to claim 10 , wherein each of the instruction buffers is adapted for storing different code.
12. The microcomputer architecture according to claim 1 , further comprising a further data register comprising a plurality of second memory units which are capable to each contain one word, the further data register being configured so that the second memory units are simultaneously accessible by the first memory unit, and at least one of the second memory units of the further data register is separately accessible by the functional unit.
13. The microcomputer architecture according to claim 12 , further comprising a demultiplexer connected between the functional unit and the further data register.
14. The microcomputer architecture according to claim 1 , wherein each word comprises a plurality of subwords, the architecture further comprising a data shifter for shifting subwords or parts of subwords so as to form a new word.
15. The microcomputer architecture according to claim 1 , wherein the microprocessor unit comprises no more than one selector for selecting words in the data register.
16. The microcomputer architecture according to claim 1 , further comprising a further functional unit, the at least part of the second memory units of the data register being separately accessible by the further functional unit.
17. The microcomputer architecture according to claim 12 , further comprising a further functional unit, the at least one of the second memory units of the further data register being separately accessible by the further functional unit.