IP Library Granted Patent US 7,193,401
Granted Patent B1
US 7,193,401 · App. 11/374,196 · Granted Mar 20, 2007

Control circuit and control method for DC-DC converter

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Quick Facts
Patent No.
US 7,193,401
App. No.
11/374,196
Granted
Mar 20, 2007
Kind
B1
Abstract

It is an object of the present invention to provide a control circuit and a control method for a current mode control type DC—DC converter capable of preventing a subharmonic oscillation even if an on-duty is not less than 50% and capable of preventing a switching frequency from fluctuating depending on an input voltage. When a high-level output signal Vo 1 is inputted to a reset input terminal R of a flip-flop FF, a transistor FET 1 is turned off. A phase comparator FC outputs a comparison result signal CONT in accordance with a phase difference between a delay signal FP and a reference signal FR. A delay circuit DLY outputs a high-level delay signal FP after the passage of a delay time DT adjusted in accordance with the comparison result signal CONT from the turn-off of the transistor FET 1 . The transistor FET 1 is turned on in accordance with an input of the high-level delay signal FP.

Claims (32)

1. A control circuit of a current mode control type DC—DC converter that controls a main switching transistor in accordance with a clock signal, comprising:

a timing adjustment circuit that outputs a timing signal for determining a timing for shifting the main switching transistor from a second state to a first state; and

a phase comparator that detects a phase difference between the timing signal and the clock signal to output a phase difference signal to the timing adjustment circuit in accordance with the phase difference, wherein

the timing adjustment circuit prolongs a delay time after the main switching transistor shifts from the first state to the second state until the timing adjustment circuit outputs the timing signal in accordance with an advance amount of a phase when the phase of the timing signal is more advanced than a phase of the clock signal, and the timing adjustment circuit shortens the delay time in accordance with a delay amount of a phase when the phase of the timing signal is delayed behind a phase of the clock signal.

2. The control circuit of a current mode control type DC—DC converter according to claim 1 , wherein

the first state is a conductive state,

the second state is a non-conductive state, and

the main switching transistor shifts from the first state to the second state in accordance with that an inductor current becomes higher than a set value.

3. The control circuit of a current mode control type DC—DC converter according to claim 1 , wherein

the first state is a non-conductive state,

the second state is a conductive state, and

the main switching transistor shifts from the first state to the second state in accordance with that an inductor current becomes lower than a set value.

4. The control circuit of a current mode control type DC—DC converter according to claim 1 , wherein

an gate input signal inputted to a gate terminal of the main switching transistor is inputted to the timing adjustment circuit, and

the timing adjustment circuit gives the delay time to an edge of the gate input signal to shift the main switching transistor from the first state to the second state, and outputs the edge given the delay time as the timing signal.

5. The control circuit of a current mode control type DC—DC converter according to claim 4 , wherein the timing adjustment circuit comprises:

a current source that changes a current amount in accordance with the phase difference signal;

a capacitor that is connected in series with the current source and of which an end is grounded;

a first switch that is brought into a non-conductive state in accordance with that the main switching transistor is brought into the second state and that is brought into a conductive state in accordance with that the main switching transistor is brought into the first state, the first switch being connected in parallel with the capacitor and the gate input signal inputted to the first switch; and

a first comparator that outputs a comparison result of a voltage of the capacitor and a first set voltage.

6. The control circuit of a current mode control type DC—DC converter according to claim 1 , wherein

the phase comparator comprises:

an integrating section;

a second switch that connects the integrating section with a grounded voltage; and

a third switch that connects the integrating section with a source voltage, and

the phase comparator makes the second switch a conductive state in accordance with an advance amount of a phase when the phase of a rising edge of the timing signal is more advanced than a phase of a rising edge of the clock signal and makes the third switch a conductive state in accordance with a delay amount of a phase when the phase of a rising edge of the timing signal is delayed behind a phase of a rising edge of the clock signal.

7. The control circuit of a current mode control type DC—DC converter according to claim 1 , further comprising a second comparator that is connected between an input terminal of a flip-flop for controlling the main switching transistor to which the timing signal is inputted and an output terminal of a DC—DC converter and that outputs the same level signal as the timing signal to the input terminal to which the timing signal is inputted in accordance with that an output voltage of the DC—DC converter exceeds a second set voltage.

8. The control circuit of a current mode control type DC—DC converter according to claim 1 , further comprising a monitoring circuit to which an error amplification signal obtained by an amplification of an error between a third set voltage and an output voltage of a DC—DC converter, a fourth set voltage and the timing signal are inputted, which inputs the timing signal to the input terminal to which the input timing signal of the flip-flop for controlling the main switching transistor is inputted in a time when the error amplification signal is higher than the fourth set voltage and that masks the timing signal in a time when the error amplification signal is lower than the fourth set voltage.

9. A control method for a current mode control type DC—DC converter for controlling a main switching transistor in accordance with a clock signal, comprising the steps of:

detecting a phase difference between a shift timing when the main switching transistor shifts from a second state to a first state and the clock signal;

shifting the main switching transistor from the first state to the second state in accordance with that an inductor current exceeds a set value after the shift of the main switching transistor to the first state; and

delaying the shift timing in accordance with an advance amount of a phase when the phase of the previous shift timing is more advanced than a phase of the clock signal, and bringing the shift timing forward in accordance with an advance amount of a phase when the phase of the previous shift timing is delayed behind a phase of the clock signal, at the subsequent determination of the shift timing.

Assignments (5)
MERGER Recorded Nov 14, 2025
From: CYPRESS SEMICONDUCTOR CORPORATION
To: INFINEON TECHNOLOGIES AMERICAS CORP.
Reel/Frame 073571/0456 →
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2013
From: FUJITSU SEMICONDUCTOR LIMITED
To: SPANSION LLC
Reel/Frame 031205/0461 →