Method of recovering digital data from a clocked serial input signal and clocked data recovery circuit

1. A method of recovering digital data from a clocked serial input signal including the steps of:

sampling the input signal with a sampling clock to obtain a sampled digital signal;

writing the sampled digital signal to a FIFO buffer with a write clock signal that has the same timing as the sampling clock;

reading a filtered output signal from the FIFO buffer with a read clock signal supplied by a phase interpolator that receives two different ones of mutually phase-shifted clock signals synchronized with the sampling clock; and

controlling the phase interpolator with a pointer monitor that monitors the write and read select pointers in the FIFO buffer to adjust the timing of the read clock signal relative to the write clock signal.

2. The method of claim 1 , wherein the pointer monitor controls the phase interpolator in a manner to force a phase step when the amount of a timing offset between the write and read select pointers in the FIFO buffer exceeds a preset limit.

3. The method of claim 2 , wherein the preset limit is determined in relation to the depth of the FIFO buffer to ensure a safety margin between write and read operations while minimizing the frequency of phase steps of the phase interpolator.

4. A clocked data recovery circuit comprising:

a sampling circuit with a signal input for application of a clocked serial input signal, a signal output and a sampling clock input for application of a sampling clock signal;

a FIFO buffer with a data input connected to the signal output of the sampling circuit, with a data output, with a write clock input to which the sampling clock is applied, and with a read clock input;

a phase interpolator with two signal inputs, a phase control input and an output connected to the read clock input of the FIFO buffer;

a multiplexer with a control input for selectively connecting the two signal inputs of the phase interpolator to two different ones of mutually phase-shifted clock signals that are synchronized with the sampling clock; and

a pointer monitor that monitors write and read select pointers in the FIFO buffer to adjust the timing of the read clock relative to the write clock so that a timing offset between the write and read select pointers in the FIFO buffer is maintained within preset limits.

5. A method of recovering digital data from a clocked serial input signal, comprising:

sampling the input signal with a sampling clock signal supplied by a first phase interpolator to obtain a sampled digital signal; the first phase interpolator being controlled to adjust the phase of the sampling clock relative to an eye of the input signal; the first phase interpolator having signal inputs connected to receive signal outputs of a voltage controlled oscillator in a phase-locked loop circuit to which a reference clock signal is applied;

writing the sampled input signal to a single-bit FIFO buffer with a write clock signal that has the same timing as the sampling clock;

reading an output signal from the FIFO buffer with a read clock signal supplied by a second phase interpolator that has signal inputs connected to receive the signal outputs of the voltage controlled oscillator in the phase-locked loop; the second phase interpolator being controlled with a pointer monitor that monitors write and read select pointers in the FIFO buffer to adjust the timing of the read clock signal relative to the write clock signal.

6. The method of claim 5 , wherein the first phase interpolator is controlled with a voting circuit to adjust the phase of the sampling clock relative to the eye of the input signal.

7. The method of claim 5 , wherein the output signal read from the FIFO buffer with the read clock signal supplied by the second phase interpolator is a filtered output signal.

8. A circuit for recovering digital data from a clocked serial input signal, comprising:

a sampling circuit for sampling the input signal with a sampling clock signal to obtain a sampled digital signal;

a first phase interpolator connected to supply the sampling clock signal to the sampling circuit;

a phase-locked loop circuit including a voltage controlled oscillator having an input connected to receive a reference clock signal and connected to supply outputs to the first phase interpolator;

a single-bit FIFO buffer connected for writing the sampled input signal with a write clock signal that has the same timing as the sampling clock; and further connected for supplying a filtered output signal by reading the written signal with a read clock signal;

a second phase interpolator connected to supply the read clock signal to the FIFO buffer; the second phase interpolator connected to receive the outputs of the voltage controlled oscillator; and

a pointer monitor connected for monitoring the write and read select pointers in the FIFO buffer to adjust the timing of the read clock signal relative to the write clock signal.

9. The circuit of claim 8 , further comprising a voting circuit connected for controlling the first phase interpolator, to adjust the phase of the sampling clock relative to an eye of the input signal.