Thin film transistor, thin film transistor panel, and method of manufacturing the same

1. A method of manufacturing a thin film transistor array panel, the method comprising:

forming a first electrode and a second electrode that are separated from each other on a substrate;

forming a silicon layer comprising amorphous silicon and polycrystalline silicon on the substrate, the silicon layer having a lower portion and an upper portion, wherein a ratio of polycrystalline silicon to amorphous silicon in the lower portion is different than a ratio of polycrystalline silicon to amorphous silicon in the upper portion;

forming a semiconductor by patterning the silicon layer;

forming a gate insulating layer on the semiconductor;

forming a third electrode to overlap the semiconductor on the gate insulating layer;

forming a passivation layer on the third electrode; and

forming a pixel electrode on the passivation layer,

wherein the upper portion is nearer to the third electrode than the lower portion, and

wherein forming the silicon layer comprises forming a seed layer utilizing a mixture gas of an inactive gas and a hydrogen gas in a reaction chamber, and then subsequently growing the silicon layer on the seed layer by introducing the inactive gas in an absence of hydrogen gas in the reaction chamber.

2. The method of claim 1 , wherein the forming of the silicon layer comprises a sputtering process that is performed utilizing a silicon target.

3. The method of claim 2 , wherein the sputtering process is performed at a deposition temperature of 250° C. to 370° C. under a working pressure of 0m Torr to 5.5m Torr.

4. The method of claim 2 , wherein the inactive gas comprises argon gas.

5. The method of claim 1 , further comprising forming an insulating element between the semiconductor and the gate insulating layer.

6. The method of claim 1 , further comprising:

forming a barrier with an opening that is placed on the pixel electrode;

forming an organic light emitting element in the opening; and

forming a common electrode on the organic light emitting element.

7. The method of claim 1 , wherein a ratio of polycrystalline silicon to amorphous silicon in the lower portion is less than a ratio of polycrystalline silicon to amorphous silicon in the upper portion.

8. The method of claim 1 , wherein a ratio of polycrystalline silicon to amorphous silicon in the silicon layer varies with respect to a distance from a surface of the silicon layer.

9. A method of manufacturing a thin film transistor array panel, the method comprising:

forming a first electrode and a second electrode that are separated from each other on a substrate;

forming a silicon layer comprising amorphous silicon and polycrystalline silicon on a surface of the substrate;

forming a semiconductor by patterning the silicon layer;

forming a gate insulating layer on the semiconductor;

forming a third electrode overlapping the semiconductor on the gate insulating layer;

forming a passivation layer on the third electrode; and

forming a pixel electrode on the passivation layer,

wherein a ratio of polycrystalline silicon to amorphous silicon in the silicon layer increases in a direction towards the third electrode from the surface of the substrate, and

wherein forming the silicon layer comprises forming a seed layer utilizing a mixture gas of an inactive gas and a hydrogen gas in a reaction chamber, and then subsequently growing the silicon layer on the seed layer by introducing the inactive gas without the hydrogen gas in the reaction chamber.