RF power amplifier system employing an analog predistortion module using zero crossings
View Patent ↗An RF amplifier system employing an analog predistortion module is disclosed. The disclosed analog predistortion module is based on zero crossings of the gain error curves (AM—AM and AM-PM curves minus DC). The hardware structure uses the product of first-order functions avoiding the need for large differential swings in the coefficients to shape the lower part of the gain curves. The higher-order nonlinear functions are preferably derived from a single envelope detector. An equal number of multipliers are preferably used in each path when the order of the magnitude and phase corrections are equal or differ by one, thus reducing delay mismatches between the magnitude and phase correction signals.
1. A linearized power amplifier system, comprising:
an input receiving an analog communication signal;
a main signal path comprising a power amplifier, and a delay circuit and a vector modulator coupled between the input and the power amplifier;
an output coupled to the output of the power amplifier;
a signal splitter coupled to the input and providing a sampled input signal on a parallel signal path to the main signal path; and
an analog baseband predistortion module configured in the parallel signal path and receiving the sampled input signal, the analog baseband predistortion module performing an analog predistortion operation employing the sampled input signal and zero crossing coefficients characterizing nonlinearity in the amplifier gain response and providing in phase and quadrature predistortion control signals to the vector modulator in said main signal path to predistort the input signal to correct for amplifier nonlinearity.
2. A linearized power amplifier system as set out in claim 1 , wherein said analog baseband predistortion module comprises an envelope detector providing an analog envelope signal corresponding to the input signal envelope and a zero crossing specification circuit performing said predistortion operation on the analog envelope signal using said zero crossing coefficients.
3. A linearized power amplifier system as set out in claim 2 , wherein said zero crossing specification circuit comprises a first plurality of addition circuits receiving zero crossing coefficients corresponding to the amplitude response of the amplifier and a second plurality of addition circuits receiving zero crossing coefficients corresponding to the phase response of the amplifier.
4. A linearized power amplifier system as set out in claim 3 , wherein said zero crossing specification circuit further comprises a plurality of multiplier circuits coupled to said first plurality of addition circuits and one or more multiplier circuits coupled to said second plurality of addition circuits.
5. A linearized power amplifier system as set out in claim 4 , wherein said first plurality of addition circuits comprises three addition circuits coupled in parallel to the envelope detector, each receiving a zero crossing coefficient, and wherein two multiplier circuits are coupled to said first plurality of addition circuits.
6. A linearized power amplifier system as set out in claim 4 , wherein said second plurality of addition circuits comprises two addition circuits coupled in parallel to the envelope detector, each receiving a zero crossing coefficient, and wherein and one multiplier circuit is coupled to said second plurality of addition circuits.
7. A linearized power amplifier system as set out in claim 2 , wherein said analog baseband predistortion module further comprises a scale and offset circuit for adjusting magnitude and phase scale and offset.
8. A linearized power amplifier system as set out in claim 7 , wherein said scale and offset circuit comprises a multiplier receiving a magnitude scaling factor, a multiplier receiving a phase scaling factor, an addition circuit receiving a magnitude offset factor, and an addition circuit receiving a phase offset factor.
9. A linearized power amplifier system as set out in claim 1 , further comprising a second signal splitter, coupled to the output and providing a sampled output signal, and an estimator, coupled to receive the sampled input signal and sampled output signal and providing said zero crossing coefficients to said analog baseband predistortion module on an adaptive basis.
10. A linearized power amplifier system as set out in claim 1 , wherein said input signal is a wide bandwidth modulated communication signal selected from the group consisting of CDMA, WCDMA and UMTS modulated RF communication signals.
11. A linearized power amplifier system, comprising:
an input receiving an analog communication signal;
a main signal path comprising a power amplifier, and a delay circuit, a magnitude adjuster and a phase adjuster coupled between the input and the power amplifier;
an output coupled to the output of the power amplifier;
a signal splitter coupled to the input and providing a sampled input signal on a parallel signal path to the main signal path; and
an analog baseband predistortion module configured in the parallel signal path and receiving the sampled input signal, the analog baseband predistortion module performing an analog predistortion operation employing the sampled input signal and zero crossing coefficients characterizing nonlinearity in the amplifier gain response and providing a magnitude adjuster control signal to the magnitude adjuster in said main signal path and a phase adjuster control signal to the phase adjuster in said main signal path to predistort the input signal to correct for amplifier nonlinearity.
12. A method for predistortion linearization of a power amplifier system comprising:
receiving an input communication signal;
splitting the input communication signal into a main input signal and a sampled input signal;
providing the main input signal to a power amplifier;
detecting the sampled input signal envelope;
generating predistortion control signals using the product of first-order functions of the sampled input signal envelope offset by zero crossing coefficients; and
applying the predistortion control signals to the main input signal prior to said amplifier to predistort the main input signal to compensate for nonlinearities in the power amplifier gain response.
13. A method for predistortion linearization of a power amplifier system as set out in claim 12 , wherein said predistortion control signals correspond to the inverse complex gain of the power amplifier.
14. A method for predistortion linearization of a power amplifier system as set out in claim 12 , wherein said zero crossing coefficients correspond to DC offsets at the locations of the intersection of a fixed AM—AM response with the actual AM—AM response curve of the power amplifier.
15. A method for predistortion linearization of a power amplifier system as set out in claim 14 , wherein said zero crossing coefficients further correspond to DC offsets at the locations of intersection of a fixed AM-PM response with the actual AM-PM response curve of the power amplifier.
16. A method for predistortion linearization of a power amplifier system as set out in claim 12 , wherein said applying the predistortion control signals to the main input signal comprises modulating the main input signal employing a vector modulator controlled by the predistortion control signals.
17. A method for predistortion linearization of a power amplifier system as set out in claim 12 , wherein said predistortion control signals comprise magnitude and phase control signals.
18. A method for predistortion linearization of a power amplifier system as set out in claim 12 , further comprising sampling the output of the power amplifier and adaptively estimating the zero crossing coefficients using the sampled input and sampled output signals.
19. A method for predistortion linearization of a power amplifier system as set out in claim 12 , further comprising delaying said main input signal prior to applying the predistortion control signals to the main input signal.
20. A method for predistortion linearization of a power amplifier system as set out in claim 12 , wherein said input signal is a wide bandwidth modulated communication signal selected from the group consisting of CDMA, WCDMA and UMTS modulated RF communication signals.