Method and/or apparatus to detect and handle defects in a memory
An apparatus comprising a memory circuit, a test circuit, an interface circuit and a defect handler circuit. The memory circuit may be configured to store and retrieve data in response to (i) a data signal, (ii) a test data signal, (iii) an address signal, (iv) a first control signal and (v) a write signal. The test circuit may be configured to generate the test data signal in response to the address signal. The interface circuit may be configured to generate the control signal in response to (i) the address signal, (ii) a read signal, and (iii) the write signal. The defect handler circuit may be configured to redirect data read from the memory circuit in response to (i) the address signal, (ii) the data signal and (iii) the write signal.
1 . An apparatus comprising:
a memory circuit configured to store and retrieve data in response to (i) a data signal, (ii) a test data signal, (iii) an address signal, (iv) a control signal and (v) a write signal;
a test circuit configured to generate said test data signal in response to said address signal;
an interface circuit configured to generate said control signal in response to (i) said address signal, (ii) a read signal, and (iii) said write signal; and
a defect handler circuit configured to redirect data read from said memory circuit in response to (i) said address signal, (ii) said data signal and (iii) said write signal.
2 . The apparatus according to claim 1 , further comprising:
a processor configured to (i) read and write data to said defect handler circuit and (ii) generate said address signal, said read signal and said write signal.
3 . The apparatus according to claim 1 , wherein said memory comprises a plurality of random access memory circuits.
4 . The apparatus according to claim 2 , wherein said test circuit generates said control signal during a boot sequence.
5 . The apparatus according to claim 3 , wherein each of said random access memory circuits comprises a plurality of memory cells.
6 . The apparatus according to claim 5 , wherein said defect handler circuit comprises a plurality of redundant memory cells configured to replace one or more of said memory cells having defects.
7 . The apparatus according to claim 6 , wherein said defect handler circuit comprising:
an address circuit configured to store said memory cells having defects;
a decoder and compare circuit configured to compare with said address signal and said-address circuit;
a redundant cell circuit comprising said plurality of redundant memory cells; and
a multiplexer circuit configured to select the redirected data read from said memory circuit.
8 . The apparatus according to claim 6 , wherein said defect handler circuit replaces a row of memory cells in response to a defect.
9 . A method for detecting and disabling defective memory cells in a memory, comprising the steps of:
(A) executing a fixed set of instructions for testing each of a number of primary cells of said memory;
(B) creating a list of addresses corresponding to a number of failed primary cells; and
(C) enabling a secondary cell for each of said failed primary cells.
10 . The method according to claim 9 , wherein said method is executed during a boot sequence of a processor that reads and writes data to said memory.
11 . The method according to claim 9 , wherein step (A) comprises enabling a row of secondary cells for a row of cells containing said failed primary cells.
12 . The method according to claim 9 , further comprising:
writing data to said secondary cells during a write operation of writing to said failed primary cells.
13 . The method according to claim 9 , further comprising:
reading data from said secondary cells during a read operation of reading from said failed primary cells.