Data transfer control device and electronic instrument
A data transfer control device includes: a link controller which analyzes a packet received through a serial bus; an interface circuit which generates interface signals and outputs the interface signals to an interface bus; and a reset signal output circuit which outputs a reset signal to the interface circuit. The link controller analyzes a packet to determine whether or not the received packet includes synchronization signal generation direction information (synchronization signal code). The reset signal output circuit outputs the reset signal to the interface circuit when the link controller has determined that the received packet includes the synchronization signal generation direction information.
1. A data transfer control device that controls data transfer, the data transfer control device comprising:
a controller that analyzes a packet received through a serial bus;
an interface circuit that generates interface signals and outputs the interface signals to an interface bus, the interface signals including a vertical synchronization signal, a horizontal synchronization signal and a data signal; and
a reset signal output circuit that outputs a reset signal of the interface circuit to the interface circuit;
the interface circuit including:
a horizontal counter that counts a horizontal synchronization cycle;
a pixel counter that counts a pixel clock cycle; and
a timing generator that outputs the vertical synchronization signal, the horizontal synchronization signal and the data signal based on a first count value from the horizontal counter and a second count value from the pixel counter,
the controller analyzing a packet received through the serial bus to determine whether or not the received packet includes synchronization signal generation direction information that directs the interface circuit to generate the vertical synchronization signal and the horizontal synchronization signal,
the reset signal output circuit outputting the reset signal to the interface circuit when the controller has determined that the received packet includes the synchronization signal generation direction information that directs the interface circuit to generate the vertical synchronization signal, and
the horizontal counter and the pixel counter being reset by the reset signals in a vertical synchronization cycle to prevent occurrence of a malfunction due to noise imposed on the serial bus.
2. The data transfer control device as defined in claim 1 ,
a packet received through the serial bus including a synchronization signal code field that sets a synchronization signal code that is the synchronization signal generation direction information,
the controller analyzing the synchronization signal code field of a packet received through the serial bus to determine whether or not the synchronization signal code that directs the interface circuit to generate the vertical synchronization signal and the horizontal synchronization signal is set in the synchronization signal code field; and
the reset signal output circuit outputting the reset signal to the interface circuit when the controller has determined that the synchronization signal code that directs the interface circuit to generate the vertical synchronization signal is set in the synchronization signal code field of the received packet.
3. The data transfer control device as defined in claim 2 ,
the controller receiving a display period packet, in which data is set in a data field, through the serial bus in a display period, and receiving a non-display period packet, in which data is not set in the data field, through the serial bus in a non-display period.
4. The data transfer control device as defined in claim 3 ,
when the controller has received the display period packet in which data is set in the data field, the controller outputting the header including the synchronization signal code set in the packet and the data set in the packet to the interface circuit, and, when the controller has received the non-display period packet in which data is not set in the data field, the controller outputting the header including the synchronization signal code set in the packet to the interface circuit.
5. The data transfer control device as defined in claim 1 , comprising:
an internal register in which timing information that specifies change timing of signal levels of the interface signals output from the interface circuit is set,
the interface circuit generating the interface signals of which the signal levels changes at timings according to the timing information based on the timing information set in the internal register.
6. The data transfer control device as defined in claim 5 ,
the timing information being set in the internal register based on a timing information packet received through the serial bus.
7. The data transfer control device as defined in claim 6 ,
the controller receiving a packet in which data is set in the data field through the serial bus after the timing information has been set in the internal register, and
the interface circuit outputting the data signal of which data is set in the packet, the vertical synchronization signal and the horizontal synchronization signal at timings according to the timing information set in the internal register.
8. The data transfer control device as defined in claim 1 , comprising:
a packet buffer into which a packet received through the serial bus is written and that outputs an N-bit signal and a 1-bit signal,
the packet buffer outputting a reset direction signal as the 1-bit signal when the controller has determined that the received packet includes the synchronization signal generation direction information, and
the reset signal output circuit outputting the reset signal to the interface circuit when the reset direction signal has been output from the packet buffer.
9. The data transfer control device as defined in claim 2 , comprising:
a packet buffer into which a packet received through the serial bus is written and that outputs an N-bit signal and a 1-bit signal,
the packet buffer outputting a reset direction signal as the 1-bit signal when the controller has determined that the received packet includes the synchronization signal generation direction information, and
the reset signal output circuit outputting the reset signal to the interface circuit when the reset direction signal has been output from the packet buffer.
10. The data transfer control device as defined in claim 5 , comprising:
a packet buffer into which a packet received through the serial bus is written and that outputs an N-bit signal and a 1-bit signal,
the packet buffer outputting a reset direction signal as the 1-bit signal when the controller has determined that the received packet includes the synchronization signal generation direction information, and
the reset signal output circuit outputting the reset signal to the interface circuit when the reset direction signal has been output from the packet buffer.
11. The data transfer control device as defined in claim 1 , the interface circuit outputting an RGB interface signal.
12. The data transfer control device as defined in claim 1 , comprising
a transceiver that transmits and receives a packet to and from a host-side data transfer control device using differential signal lines of the serial bus.
13. An electronic instrument comprising:
the data transfer control device as defined in claim 1 ; and
a device connected with the data transfer control device through the interface bus.
14. An electronic instrument comprising:
the data transfer control device as defined in claim 2 ; and
a device connected with the data transfer control device through the interface bus.
15. An electronic instrument comprising:
the data transfer control device as defined in claim 5 ; and
a device connected with the data transfer control device through the interface bus.
16. An electronic instrument comprising:
the data transfer control device as defined in claim 8 ; and
a device connected with the data transfer control device through the interface bus.
17. The data transfer control device as defined in claim 1 , comprising:
an internal register in which timing information that specifies change timings of signal levels of the vertical synchronization signal, the horizontal synchronization signal and the data signal output from the interface circuit are set,
the interface circuit adjusting actual change timings of the vertical synchronization signal, the horizontal synchronization signal and the data signal based on the timing information set in the internal register, the first count value from the horizontal counter and the second count value from the pixel counter when the packet including the synchronization signal generation direction information is received.
18. The data transfer control device as defined in claim 17 ,
the interface circuit performing decode processing based on the first count value from the horizontal counter and the second count value from the pixel counter to generate the vertical synchronization signal, the horizontal synchronization signal and the data signal.
19. The data transfer control device as defined in claim 17 ,
the timing information being set in the internal register based on a timing information packet received through the serial bus from a host-side data transfer device.
20. The data transfer control device as defined in claim 17 ,
the synchronization signal generation direction information being received through the serial bus from a host-side data transfer device,
the host-side data transfer device receiving a host-side vertical synchronization signal, a host-side horizontal synchronization signal and a host-side data signal from a host,
the host-side data transfer device setting the synchronization signal generation direction information indicating direction of generating the vertical synchronization signal when the host-side vertical synchronization from the host is detected,
the host-side data transfer device setting the synchronization signal generation direction information indicating direction of generating the horizontal synchronization signal when the host-side horizontal synchronization from the host is detected, and
the interface circuit generating the vertical synchronization signal, the horizontal synchronization signal and the data signal as the reproduction signals of the host-side vertical synchronization signal, the host-side horizontal synchronization signal and the host-side data signal based on the timing information.