Multi-master, chained two-wire serial bus

1. A multi-master and chained two-wire serial bus, comprising:

a host two-wire serial bus, including: a first master device;

one or more slave devices coupled to the first master device, each slave device operable to send data to and receive data from the first master device; and one or more chained two-wire serial busses coupled to the host two-wire serial bus,

comprising: a second master device, the second master device also being a slave device on the host two-wire serial bus, the second master device operable to send data to and receive data from the first master device; and one or more other slave devices coupled to the second master device, each other slave device operable to send data to and receive data from the second master device; wherein the second master device comprises an emulation memory operable to: store data received from the first master device or received from the one or more other slave devices and to emulate data stored at one or more of the other slave devices on one of the chained two-wire serial busses; and wherein the emulation memory stores the same type and amount of data and at the same address and offset as the one or more slave devices on the one of the chained two-wire serial busses.

2. The multi master and chained two-wire serial bus apparatus as defined in claim 1 , wherein the first master device completes a two-wire serial transaction with the second master device to write data to or read data from the one or more other slave devices.

3. The multi master and chained two-wire serial bus apparatus as defined in claim 1 , further comprising one or more other chained two-wire serial bus coupled to the one or more chained two-wire serial busses, including: a third master device, the third master device also being a slave device on the chained two-wire serial bus, the third master device operable to send data to and receive data from the second master device; and one or more further slave devices coupled to the third master device, each further slave device operable to send data to and receive data from the third master device.

4. The multi master and chained two-wire serial bus apparatus as defined in claim 1 , wherein the second master device is a digital state machine.

5. A digital state machine operable to emulate both a two-wire serial master device and a two-wire serial slave device on chained two-wire serial busses, comprising:

a two-wire serial slave component, the two-wire serial slave component operable to send data to and receive data from a master device on a host two-wire serial bus; a two-wire serial master component, the two-wire serial master component operable to send data to and receive data from one or more slave devices on a second two-wire serial bus; and an emulation memory component coupled to the two-wire serial slave component and coupled to the two-wire serial master component, the emulation memory component operable to: store data received from a master device on the host two-wire serial bus or received from a slave device on the second two-wire serial bus, and to emulate data stored at one or more slave devices on the second two-wire serial bus, wherein the emulation memory stores the same type and amount of data and at the same address and offset as the one or more slave devices on the second two-wire serial bus.

6. The digital state machine as defined in claim 5 , wherein the two-wire serial slave component emulates a two-wire serial transaction with the master device on the host two-wire serial bus.

7. The digital state machine as defined in claim 6 , wherein during the emulated two-wire serial transaction the two-wire serial slave component writes data to or reads data from the emulation memory.

8. The digital state machine as defined in claim 5 , wherein two-wire serial master component emulates a two-wire serial transaction with a slave device on the second two-wire serial bus.

9. The digital state machine as defined in claim 8 , wherein during the emulated two-wire serial transaction the two-wire serial master component writes data to or reads data from the emulation memory.

10. A method for transferring data between a first device on a first two-wire serial bus and a second device on a second two-wire serial bus, the method comprising:

receiving data from the first device on the first bus; storing the data in an emulation memory in a digital state machine, the emulation memory having a format which matches a format of the first device, the data being stored in the emulation memory as per the format;

extracting the data from the emulation memory to send to the second device on the second bus; and sending the data to the second device on the second bus, wherein a format of the emulation memory which matches the format of the first device comprises one of (i) a same address, and (ii) a same offset.

11. A method as defined in claim 10 , wherein the first device is a master device, the first bus is a host two-wire serial bus, the second device is a slave device, and the second two-wire serial bus is a chained two-wire serial bus that is chained to the host two-wire serial bus.

12. A method as defined in claim 11 , wherein receiving data further comprises: receiving a START condition; receiving an address for the second device; receiving a WRITE signal; sending an acknowledge signal from a two-wire serial slave component, in the digital state machine, coupled to the master device on the host two-wire serial bus; receiving one or more data words at the two-wire serial slave component; and receiving a STOP condition.

13. A method as defined in claim 11 , wherein sending data further comprises: issuing a START condition from a two-wire serial master component in the digital state machine; sending an address for the slave device; sending a WRITE signal; receiving an acknowledge signal; sending one or more data words from the two-wire serial master component to the slave device; and issuing a STOP condition.

14. A method as defined in claim 10 , wherein the first device is a slave device, the first bus is a chained two-wire serial bus, the second device is a master device, and the second two-wire serial bus is a host two-wire serial bus, wherein the chained two-wire serial bus is chained to the host two-wire serial bus.

15. A method as defined in claim 14 , wherein data is periodically received, from the one or more slave devices, and stored in the emulation memory.

16. A method as defined in claim 14 , wherein receiving data further comprises: issuing a START condition from a two-wire serial master component in the digital state machine; sending an address for the slave device; sending a READ signal; receiving an acknowledge signal; receiving one or more data words at the two-wire serial master component from the slave device; and issuing a STOP condition.

17. A method as defined in claim 14 , wherein sending data further comprises: receiving a START condition at a two-wire serial slave component coupled to the master device; receiving an address for the slave device; receiving a READ signal; sending an acknowledge signal from the two-wire serial slave component; sending one or more data words from the two-wire serial slave component to the master device; and receiving a STOP condition.