IP Library Granted Patent US 7,345,308
Granted Patent B2
US 7,345,308 · App. 11/379,879 · Granted Mar 18, 2008

Solid-state imaging device

Assignee: Seiko Epson Corporation
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,345,308
App. No.
11/379,879
Granted
Mar 18, 2008
Kind
B2
Abstract

A solid-state imaging device includes: a photoelectric conversion element; a pixel region including a modulation part formed adjacent to the photoelectric conversion element; and a peripheral region in which a peripheral circuit including a driving circuit driving the photoelectric conversion element and the modulation part is disposed, wherein the peripheral region includes a transistor that a sidewall is formed on a side of a gate electrode; and the pixel region includes a transistor that no sidewall is formed on a side of a gate electrode.

Claims (16)

1. A solid-state imaging device, comprising:

a photoelectric conversion element;

a pixel region including a modulation part formed adjacent to the photoelectric conversion element; and

a peripheral region in which a peripheral circuit including a driving circuit driving the photoelectric conversion element and the modulation part is disposed, wherein the peripheral region includes a transistor that a sidewall is formed on a side of a gate electrode; and

wherein the pixel region includes:

a transistor that no sidewall is formed on a side of a gate electrode;

a substrate of one conductivity type;

a first impurity layer of a reverse conductivity type formed on the substrate;

a second impurity layer of one conductivity type formed on the first impurity layer in a forming region of the photoelectric conversion element;

a third impurity layer of one conductivity type formed on the first impurity layer in a forming region of the transistor, photo-generated charges being transferred to the third impurity layer from the second impurity layer;

a gate electrode formed above the third impurity layer above the substrate, the gate electrode having an opening and no sidewall on a side thereof;

a source formed on a surface side of the substrate in the opening; and

a drain formed apart from the source and electrically coupled to the first impurity layer.

2. The solid-state imaging device according to claim 1 , wherein the gate electrode is formed in a ring-shape.

3. The solid-state imaging device according to claim 1 , further comprising:

a fourth impurity layer formed under the gate electrode in the third impurity layer so as to be highly doped than the third impurity layer.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 28, 2019
From: SEIKO EPSON CORPORATION
To: 138 EAST LCD ADVANCEMENTS LIMITED
Reel/Frame 050197/0212 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 24, 2006
From: SAKANO, YORITO; MIZUGUCHI, AKIRA; NAKAMURA, NORIYUKI
To: SEIKO EPSON CORPORATION
Reel/Frame 017518/0395 →
Priority Claims (1)
JP 2005-140734 · May 13, 2005 · national
Continuity (1)
Related Publication 20060290659A1 · Dec 28, 2006