Integrated circuit with reduced analog coupling noise
View Patent ↗An integrated circuit includes CMOS circuit blocks and analog control lines arranged outside a layout of the CMOS circuit blocks so that the analog wiring and circuit blocks do not overlap each other. The distance of signal lines within a circuit block and the analog control lines can become as long as necessary, and the signal line within the circuit block and the analog control lines are not coupled via parasitic capacitance, and mutual interference is suppressed. In another aspect, a method of arranging a semiconductor integrated circuit includes providing a plurality of functional circuit blocks and connecting analog control wiring to the functional circuit blocks. The analog control wiring is arranged outside a layout of the functional circuit blocks on the semiconductor integrated circuit so that the analog control wiring does not overlap any one of the functional circuit blocks so as to reduce or eliminate interference between signal lines within a circuit block and the analog control lines.
1. A semiconductor integrated circuit, comprising:
CMOS circuit blocks;
analog control lines connected to said CMOS circuit blocks;
wherein said analog control lines are arranged outside a layout of said CMOS circuit blocks so that said CMOS circuit blocks and said analog control lines do not overlap each other.
2. The semiconductor integrated circuit of claim 1 , wherein said CMOS circuit blocks comprise:
a control circuit; an AM block, and an FM block,
wherein the analog control lines are connected between the control circuit and each of the AM block and the FM block.
3. The semiconductor integrated circuit of claim 2 , wherein said CMOS circuit blocks further comprise an AM/FM common block connected to the analog control lines.
4. A semiconductor integrated circuit, comprising:
a plurality of CMOS circuit blocks each having an ON/OFF function relating to a power source;
analog control lines connected to the plurality of CMOS circuit blocks and arranged to provide control of said ON/OFF function for one or more of the plurality of CMOS circuit blocks; wherein said analog control lines are wired outside a layout of said plurality of CMOS circuit blocks so that any wiring associated with said plurality of CMOS circuit blocks and said analog control lines do not overlap each other, and wherein said control circuit controls the ON/OFF function of each of the plurality of CMOS circuits so as to conserve electrical power in the semiconductor integrated circuit.
5. The semiconductor integrated circuit of claim 4 , further comprising a control circuit connected to the plurality of CMOS circuit blocks by said analog control lines.
6. The semiconductor integrated circuit of claim 4 , wherein said plurality of CMOS circuit blocks comprise an AM block, and an FM block,
wherein the analog control lines are connected between the control circuit and each of the AM block and the FM block.
7. The semiconductor integrated circuit of claim 6 , wherein said plurality of CMOS circuit blocks further comprise an AM/FM common block connected to the analog control lines.
8. A method of arranging a semiconductor integrated circuit, the method comprising:
providing a plurality of functional circuit blocks;
connecting analog control wiring to said functional circuit blocks;
arranging said analog control wiring outside a layout of said functional circuit blocks on the semiconductor integrated circuit so that said analog control wiring does not overlap any one of the plurality of functional circuit blocks.
9. The method of claim 8 , wherein the plurality of functional circuit blocks comprise an AM block, and FM block, and a control block, the method further comprising:
controlling an operation of each of the plurality of functional circuit blocks responsive to control signals provided by the control unit through the analog control wiring.
10. A method of controlling electrical interference in a semiconductor integrated circuit comprising a plurality of CMOS circuit blocks each having an ON/OFF function with respect to a power source, the method comprising:
arranging analog control wiring connected to said CMOS circuit blocks outside a layout area of said plurality of CMOS circuit blocks on the semiconductor integrated circuit; and
ensuring that said analog control wiring does not overlap any of the plurality of CMOS circuit blocks.
11. The method of claim 10 , further comprising controlling the ON/OFF function of each of the plurality of CMOS circuit blocks so as to reduce consumption of electrical power by the semiconductor integrated circuit.